1. Spike Sorting Algorithm Implemented on FPGA Elad Ilan Asaf Gal Sup: Alex Zviaginstev

2. Goals & Targets Implement a detect & sort algorithm of Neural spike on FPGA. Explore different algorithmic options and implementations for better performance.

3. The general system

4. Requirements Low frequency: ~100KHz input rate. Small H/W as possible Very low power consumption Low output rate as possible

5. Algorithm overview Learning phase: Apply PCA algorithm on a set of learning data Extract best separation lines from the learning data. Store separation lines parameters in chip registers.

6. Algorithm overview Real time sorting: Apply threshold detection to raw data Calculate speculative projections on PC space, for a set of predefined alignments. Find the most suitable alignment (maximum find) Sort the spike by comparing to separation lines

7. Algorithm overview

8. Interface

9. Operation modes LDPC mode: In this mode PC data is loaded into internal registers. The data is input on the SPKDATA pin, and the PC index is set by PCSEL pin (‘0’ – PC1, ‘1’ – PC2). The registers depth is the same as the spike length. WRCR mode: In this mode the unit updates the control register with address on pin CRADDR with the value on pin CRDATA. RDCR mode: In this mode the value in the CR with address on pin CRADD is written to output pin CRDATAOUT SORT mode: In this mode unit sorts the spike data on pin SPKDATA. IDLE mode: In this mode no operation is done in the unit. CR values are kept. RST

10. Implementation Block diagram:

11. Implementation Detection block:

12. Implementation Extraction block:

13. Implementation Sorting block:

14. Implementation Control block:

15. Implementation Pipeline diagram

16. Implementation Pipeline diagram

17. H/W characterization 100KHz input rate  20MHz internal clock freq. 40 input data pins 27 output pins W/C output rate: 500Hz x 19 pins # of logic gates: ??? # of seq. elements: ~5K

18. Environment

19. Current status HDL code written Only partly validated. Environment almost ready (for HDL model)

20. Till end of Jan: Validation finished First simulation Initial syn runs Initial P&R H/W order Validation finished February – Asaf in RD Future time line

21. Back up Foils