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D Flip-Flops in Verilog Discussion 10.3 Example 27
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// Example 27a: D flip-flop with clear module Dff ( input wire clk, input wire clr, input wire D, output reg q ); always @(posedge clk or posedge clr) if(clr == 1) q <= 0; else q <= D; endmodule
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Aldec Active-HDL Simulation
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// Example 27b: D flip-flop with set and clear module Dffsc ( input wire clk, input wire clr, input wire set, input wire D, output reg q ); always @(posedge clk or posedge clr or posedge set) if(set == 1) q <= 1; else if(clr == 1) q <= 0; else q <= D; endmodule
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Aldec Active-HDL Simulation
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