1. Spring 07, Jan 30 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 SOC Test Scheduling Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07

2. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)2 Power Considerations in Design  A circuit is designed for certain function. Its design must allow the power consumption necessary to execute that function.  Power buses are laid out to carry the maximum current necessary for the function.  Heat dissipation of package conforms to the average power consumption during the intended function.  Layout design and verification must account for “hot spots” and “voltage droop” – delay, coupling noise, weak signals.

3. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)3 Testing Differs from Functional Operation VLSI chip system System inputs System outputs Functional inputs Functional outputs Other chips

4. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)4 Basic Mode of Testing VLSI chip Test vectors: Pre-generated and stored in ATE DUT output for comparison with expected response stored in ATE Automatic Test Equipment (ATE): Control processor, vector memory, timing generators, power module, response comparator Power Clock Packaged or unpackaged device under test (DUT)

5. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)5 Functional Inputs vs. Test Vectors  Functional inputs:  Functionally meaningful signals  Generated by circuitry  Restricted set of inputs  May have been optimized to reduce logic activity and power  Test vectors:  Functionally irrelevant signals  Generated by software to test faults  Can be random or pseudorandom  May be optimized to reduce test time; can have high logic activity  May use testability logic for test application

6. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)6 An Example VLSI chip Binary to decimal converter 3-bit random vectors 8-bit 1-hot vectors VLSI chip system VLSI chip in system operation VLSI chip under test High activity 8-bit test vectors from ATE

7. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)7 Reducing Comb. Test Power 1 1 0 0 0 1 0 1 0 0 1 0 1 0 1 1 0 1 1 1 V1V2V3 V4V5 34 1 3 2 2 3 2 1 1 V1 V2 V3 V4 V5 10 input transitions Traveling salesperson problem (TSP): Find the shortest distance closed path (or cycle) to visit all nodes exactly once. V1 V3 V5 V4 V2 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 5 input transitions

8. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)8 Open-Loop TSP  Add a node V0 at distance 0 from all other nodes.  Solve TSP for the new graph.  Delete V0 from the solution. V1V2V3 V4V5 34 1 3 2 2 3 2 1 1 V0 0 0 0 0 0

9. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)9 Traveling Salesperson Problem  A. V. Aho, J. E. Hopcroft anf J. D. Ullman, Data Structures and Algorithms, Reading, Massachusetts: Addison-Wesley, 1983.  E. Horowitz and S. Sahni, Fundamentals of Computer Algorithms, Computer Science Press, 1984.

10. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)10 Scan Testing Combinational logic Scan flip- flops Primary inputs Primary outputs Scan-in SI Scan-out SO Scan enable SE DFF mux SE SI D D D’ SO 1010

11. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)11 Example: State Machine S5 S1 S4 S2 S3 Reduced power state encoding S1 = 000 S2 = 011 S3 = 001 S4 = 010 S5 = 100 State transition Comb. Input changes 000 → 001 1 000 → 100 1 011 → 010 1 001 → 011 1 010 → 000 1 100 → 010 2 Functional transitions

12. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)12 Scan Testing of State Machine Combinational logic FF=0 FF=1 Primary inputs Primary outputs Scan-in 010 Scan-out 100 State transition Comb. Input changes 100 → 010 2 010 → 101 3 101 → 010 3 Test transitions

13. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)13 Low Power Scan Flip-Flop DFF mux SE SI D DFF mux SE SI D SO D’ SO Scan FF cellLow power scan FF cell 1010

14. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)14 Built-In Self-Test (BIST) Linear feedback shift register (LFSR) Multiple input signature register (MISR) Circuit under test (CUT) Pseudo-random patterns Circuit responses BIST Controller Clock C. E. Stroud, A Designer’s Guide to Built-In Self-Test, Boston: Kluwer Academic Publishers, 2002.

15. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)15 Test Scheduling Example R1R2 M1 M2 R3R4 A datapath

16. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)16 BIST Configuration 1: Test Time LFSR1LFSR2 M1 M2 MISR1MISR2 Test time Test power T1: test for M1 T2: test for M2

17. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)17 BIST Configuration 2: Test Power R1LFSR2 M1 M2 MISR1MISR2 Test time Test power T1: test for M1 T2: test for M2

18. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)18 Testing of MCM and SOC  Test resources: Typically registers and multiplexers that can be reconfigured as test pattern generators (e.g., LFSR) or as output response analyzers (e.g., MISR).  Test resources (R1,...) and tests (T1,...) are identified for the system to be tested.  Each test is characterized for test time, power dissipation and resources it requires.

19. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)19 Resource Allocation Graph T1T2T3T4T5T6 R2R1R3R4R5R6R7R8R9

20. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)20 Test Compatibility Graph (TCG) T1 (2, 100) T2 (1,10) T3 (1, 10) T4 (1, 5) T5 (2, 10) T6 (1, 100) Tests that form a clique can be performed concurrently. Power Test time Pmax = 4

21. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)21 Test Scheduling Algorithm  Identify all possible cliques in TCG:  C1 = {T1, T3, T5}  C2 = {T1, T3, T4}  C3 = {T1, T6}  C4 = {T2, T5}  C5 = {T2, T6}  Break up clique sets into power compatible sets (PCS), that satisfy the power constraint.

22. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)22 Test Scheduling Algorithm...  PCS (Pmax = 4), tests within a set are ordered for decreasing test length:  C1 = {T1, T3, T5} → (T1, T3), (T1, T5), (T3, T5)  C2 = {T1, T3, T4} → (T1, T3, T4)  C3 = {T1, T6} → (T1, T6)  C4 = {T2, T5} → (T2, T5)  C5 = {T2, T6} → (T2, T6)  Expand PCS into subsets of decreasing test lengths. Each subset is an independent test session, consisting of tests that can be concurrently applied.  Select test sessions to cover all tests such that the added time of selected sessions is minimum.

23. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)23 TS Algorithm: Cover Table Test sessions T1T2T3T4T5T6Length (T1, T3, T4) XXX100 (T1, T5) XX100 (T1, T6) XX100 (T2, T6) XX100 (T3, T5) XX10 (T2, T5) XX10 (T3, T4) XX10 (T5)X10 (T4)X5 Selected sessions are (T3,T4), (T2, T5) and (T1, T6). Test time = 120.

24. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)24 A System Example: ASIC Z* RAM 2 Time=61 Power=241 RAM 3 Time=38 Power=213 ROM 1 Time=102 Power=279 ROM 2 Time=102 Power=279 RAM 1 Time=69 Power=282 RAM 4 Time=23 Power=96 Reg. file Time = 10 Power=95 Random logic 1, time=134, power=295 Random logic 2, time=160, power=352 *Y. Zorian, “A Distributed Control Scheme for Complex VLSI Devices,” Proc. VLSI Test Symp., April 1993, pp. 4-9.

25. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)25 Test Scheduling for ASIC Z 1200 900 600 300 Power Power limit = 900 0 100 200 300 400 Test time 331 RAM 1 RAM 3 Random logic 2 Random logic 1 ROM 2 ROM 1 RAM 2 Reg. file RAM 4 R. M. Chou, K. K. Saluja and V. D. Agrawal, “Scheduling Tests for VLSI Systems under Power Constraints,” IEEE Trans. VLSI Systems, vol. 5, no. 2, pp. 175-185, June 1997.

26. Spring 07, Jan 30ELEC 7770: Advanced VLSI Design (Agrawal)26 References  N. Nicolici and B. M. Al-Hashimi, Power- Constrained Testing of VLSI Circuits, Boston: Kluwer Academic Publishers, 2003.  E. Larsson, Introduction to Advanced System- on-Chip Test Design and Optimization, Springer 2005.