1. UCSB Silicon Workshop: SVX3D Ankush Mitra Academia Sinica SVX3D Introduction Initialisation Front-End / Acquisition Digitisation Readout Using the chip Summary

2. 11 May 06UCSB Silicon Workshop: SVX3D2 Warning!!!!!! This talk is based on the chip manual, other (sparse!) chip documents and my intuition 6 Years old with no update

3. 11 May 06UCSB Silicon Workshop: SVX3D3 SVX3D Introduction

4. 11 May 06UCSB Silicon Workshop: SVX3D4 Where is the SVX3D? SVX3D reads out the charge from the Silicon sensor Each chip (+hybrid) is attached to the Silicon sensors There are ~5,000 chips in SVX-II

5. 11 May 06UCSB Silicon Workshop: SVX3D5 SVX3D 128 Analog Integrators 47 Deep Analog Pipeline X 128 Digitisation & Sparsification 53 MBytes/s Data Out Analog (Front End)Digital (Back end) 128 Silicon Strips “2 Chips” in one Analog Front End Digital Back End Many programmable features Can read out N and P type Silicon strips Multiple chips can be daisy-chained 7.56MHz (132ns period) FECLK 53MHz (19ns period) BECLK

6. 11 May 06UCSB Silicon Workshop: SVX3D6 SVX3D Daisy Chain TNBR/BNBR allow inter-chip communication Has multiple roles Data Lines and Control lines share a common bus Data Lines have multiple roles Bus 0 – Bus 7 + OBDV Chip Control Lines

7. 11 May 06UCSB Silicon Workshop: SVX3D7 Chip Modes Initialisation : Front-End & Back-End Setup SVX3D SET DEFAULTS in SVXDAQ CONFIG in Run Control Acquisition : Front-End Collect charge from the sensor and store it on the pipeline Digitisation : Back-End Digitise the channels Readout : Back-End Send data out of chip Acquisition Digitisation Readout time Initialisation Front End Back End SVX3D can collect charge and digitise simultaneously

8. 11 May 06UCSB Silicon Workshop: SVX3D8 Initialisation

9. 11 May 06UCSB Silicon Workshop: SVX3D9 Initialisation: Single Chip SVX3D has many programmable features Need to initialise chip before it can be used for data taking Sent as a 197 bit serial bit stream Data is sent in through TNBR and clocked on FECLK Use CALSR to latch in shadow register 197 Bit Serial Shift Register TNBR BNBR FECLK Shadow Register Test Inputs 128 CALSR Adjustable Chip Parameter 69

10. 11 May 06UCSB Silicon Workshop: SVX3D10 Initialisation: Daisy Chain In daisy chain, TNBR/BNBR link shift registers of all chips together For a daisy chain of chip, send N chip x 197 bits So first bit sent ends up in last chip in chain (chip 0) Chip 3Chip 2Chip 1Chip 0

11. 11 May 06UCSB Silicon Workshop: SVX3D11 Initialisation: What can be set Read Neighbours (163) Read All (164) ADC Ramp Dir (165) ADC Comp Dir(166) Ramp Slope Trim (167- 174) Threshold (175-182) Counter Modulo (183- 190) RDriver (191-193) ADC Ramp Pedestal (194-197) Channel Mask (1-128) CAL Direction (129) FE Polarity (130) Bandwidth (131-133) Pipeline Depth (134- 139) ISEL (140-150) Readout Order(151) Chip ID (152-158) DPS (159) Bias Ratio (160) Driver Bias (161) Last chip (162)

12. 11 May 06UCSB Silicon Workshop: SVX3D12 Front End / Acquisition

13. 11 May 06UCSB Silicon Workshop: SVX3D13 Front End All 128 channels acquire charge simultaneously Each channel implements same circuit Collected charge is transferred onto analog pipeline Integrator Analog Pipeline X128 for 1 chip

14. 11 May 06UCSB Silicon Workshop: SVX3D14 Front End: Integrator Charge from sensor Test Charge: Polarity set by CALDIR Integrator reset: Controlled by PARST Only applied in abort gap During bunch crossings, charge on integrator capacitor is allowed to build up cfcf Charge on c f time Bunch train collision Bandwidth set by initialisation bits

15. 11 May 06UCSB Silicon Workshop: SVX3D15 Acquisition: Pipeline c1c1 c2c2 c 47 Read Amp Write Amp Pipeline logic controls pipeline switches This capacitor store the charge on c f from previous bunch crossing Only difference of charge on c f and c c is transferred to pipeline cell c n c 47 Cells in pipeline 42 cells for L1A latency 4 L1A buffers 1 Reference capacitor (only filled in abort gap) Initialisation bits set Pipeline operating currents, polarity and pipeline depth

16. 11 May 06UCSB Silicon Workshop: SVX3D16 Acquisition: Pipeline logic All pipeline capacitor cells are filled in a round-robin fashion Advanced by FECLK If a L1A is received pipeline cell n-(L1 latency) is reserved This cell is skipped over and only returned to pipeline after it is digitised (done by PRD2 signal) Only 4 cells can be tagged (4 L1 buffers) During abort gap, pipeline cell 47 is set Pipeline circular buffer Write pointer Tagged Cell

17. 11 May 06UCSB Silicon Workshop: SVX3D17 Back End / Digitisation

18. 11 May 06UCSB Silicon Workshop: SVX3D18 Digitisation: Subtraction of Pedestal Write Amp Read Amp c1c1 c2c2 c 47 PRD1 used to transfer charge from pipeline If READOUT ORDER=0 First PRD1 puts cell 47 on c s (pedestal) Second PRD1 reads out c n (signal+pedestal) pedestal – (signal+pestal) transferred For READOUT ORDER=1, the order is reversed cscs To ADC

19. 11 May 06UCSB Silicon Workshop: SVX3D19 Digitisation: Wilkinson ADC Conversion of analog charge to digitised value is performed by Wilkinson-type ADC V IN1 V IN3 V IN2 RAMP-RST starts a common voltage ramp CNTR-RST starts a common 8 bit counter Incremented by both edges of BECLK When voltage- ramp=V IN,m comparator fires Latch locks current counter value

20. 11 May 06UCSB Silicon Workshop: SVX3D20 Digitisation: ADC Setting From the initialisation, many of the ADC parameters can be adjusted Direction of ramp set by ADC RAMP DIRECTION Ramp Reference is set by Ramp Pedestal + ADC RAMP PEDESTAL (can be +ve or –ve) Slope of ramp can trimmed by ADC SLOPE TRIM Comparator can trigger off rising or falling edges: Set by ADC COMPARATOR DIRECTION Maximum value of counter is set by COUNTER MODULO Bias current of comparator and voltage ramp op-amp can be adjusted by BIAS RATIO Ramp Pedestal Ramp Reference t V Start counter 0 signal level signal level Digitised value Latch counter Position of start counter determines where 0 ADC counts sits

21. 11 May 06UCSB Silicon Workshop: SVX3D21 Digitisation: Dynamic Pedestal Subtraction Method to calculate common mode pedestal in real time by delaying start of counter. DPS works if: Low hit occupancy Uniform pick up across all 128 channels Once N comparators have fired, counter starts Channels near pedestal will fire first V Threshold set externally via resistor External resistor set to 7k   35 Channels need to fire CDF Note 4852 All channels are capacitively coupled

22. 11 May 06UCSB Silicon Workshop: SVX3D22 Digitisation: Threshold & Sparsification If in NN or Sparse mode, channels with ADC value > Threshold are read out If Threshold > COUNTER MODULO: No channels read out In NN mode adjacent channels are read out If channel 0 or 127 are hit, neighbour information is passed via TNBR & BNBR respectively Before Readout, each hit channel is stacked into asynchronous FIFO for fast readout ~600ns needed for FIFO to collapse

23. 11 May 06UCSB Silicon Workshop: SVX3D23 Front End / Readout

24. 11 May 06UCSB Silicon Workshop: SVX3D24 Readout: Data Format Data is transmitted in 1 Byte chunks. Always accompanied with Odd-Byte-Data- Valid (OBDV) Signal Chip ID Cap-ID (Only lower 6 bits used) Channel (Binary) Data (Gray) Channel (Binary) Data (Gray)

25. 11 May 06UCSB Silicon Workshop: SVX3D25 Readout: Multiple Chips Priority of chip readout is passed down via TNBR/BNBR lines In this example, Chip 3 is read out first and then the others First channel, first chip and last chip, last channel are always read out Q: How does the chip do this ? Not mentioned in chip manual Readout token passed along chip chain Chip 3 readout first Chip 0 readout last

26. 11 May 06UCSB Silicon Workshop: SVX3D26 Experience with SVX3D

27. 11 May 06UCSB Silicon Workshop: SVX3D27 Chip Features During detector commissioning, a number of features were found Keep Alive Every 270s, PRD2 and BE Clock has to be sent, if no other command has been sent No keep alive: chip goes into high current state and trips off Mini Digitise At end of readout, send extra BE Clocks (& maybe other signals?) Why? Works better if you do it (Tom Zimmerman – SVX3D father) Abort Digitise disabled Was implemented to stop digitisation early. Found to make chip go into a high current state. Now SRC & FIB protect against this Need to reinitialise from time to time 1 chip consumes 80-100mA on AVDD Sometimes AVDD drops 1 chip of current spontaneously during data taking Need to reinitialise chip chain (HRR)

28. 11 May 06UCSB Silicon Workshop: SVX3D28 Chip Problems: AVDD2 Failure CAP-ID is sometime indicator an impending AVDD2 failure Behaviour can be reproduced by removing AVDD2 bond Chips draws power parasitically from DVDD “Finger” connects hybrid and chip via silver epoxy joint Some AVDD2 Failures do recover Observed Symptoms 1. Loss of communication to chip front- end 2. Increase in DVDD current 3. Chip chain broken after affected chip 4. Failure observed after beam incidents (or when ladder temperature changes) bonds epoxy finger

29. 11 May 06UCSB Silicon Workshop: SVX3D29 SVX3D Summary All Silicon ladders readout by SVX3D chip Integrated Analog Front-End and Digital Back-End Dead-timeless: Can collect charge and digitise simultaneously Honeywell Rad-Hard CMOS 0.8m Process 4 MRads with Co 60 Source 15 MRads with 55MeV Proton Source Fast: Capable of running at 132ns clock rates Dynamic Pedestal Subtraction Subtracts common mode noise Sparsification Removes channels below programmable threshold Reduces data-rate and readout time 128 Analog Integrators 47 Deep Analog Pipeline Digitisation & Sparsification 53MBytes/s Data Out Analog (Front End) Digital (Back end) 128 Silicon Strips

30. 11 May 06UCSB Silicon Workshop: SVX3D30 Backup

31. 11 May 06UCSB Silicon Workshop: SVX3D31 SVX3D Floor plan 128 Inputs Analog Power Calibration Voltage Digital Power 8 Bit Data Bus + OBDV Chip control lines Bottom Neighbour Top Neighbour A number of lines have multiple roles

32. 11 May 06UCSB Silicon Workshop: SVX3D32 Acquisition: Pipeline Timing FECLK clock used to advance pipeline FECLK coincides with beam-crossing Difference of c f and c c is transferred to pipeline cell c n FECLK Advance pipeline Pipeline cell c n+1 is reset c c stores charge from previous bunch crossing

33. 11 May 06UCSB Silicon Workshop: SVX3D33 Initialisation: SVXDAQ Chip ID (152-158) Threshold (175- 182) Pipe Depth (134- 139) Ramp Trim (167- 174) Bandwidth (131- 133) Counter Mod (183- 190) Ramp Pedestal (194-197)

34. 11 May 06UCSB Silicon Workshop: SVX3D34 Initialisation: SVXDAQ Pipe Sel (130) Cal Dir (129) Readout Order (151) Comp Dir (166) Ramp Dir (165) Last Chip (162) Readout Mode (163,164) Predefined settings for polarity

35. 11 May 06UCSB Silicon Workshop: SVX3D35 Initialisation: SVXDAQ Calibration Masks for each channel Set bit to 1 for channel to be readout for calibration

36. 11 May 06UCSB Silicon Workshop: SVX3D36 Initialisation: SVXDAQ ISEL Bits (140- 150) Program currents for FE Op-Amps

37. 11 May 06UCSB Silicon Workshop: SVX3D37 Initialisation: SVXDAQ Driver Com Mode (161) Bias Ratio (160) Dynamic Threshold (159) Resistor Driver (191-193)

38. 11 May 06UCSB Silicon Workshop: SVX3D38 Readout Data is output via tri-stated 8 bit parallel bus Can operate in Current driver or Resistor driver mode The resistors in the driver are switch on/off via the RDriver values MSB: Adds 6.3mA Mid Bit: Adds 3.3mA LSB: Adds 1.7mA Driver Com Mode adjusts V Ref

39. 11 May 06UCSB Silicon Workshop: SVX3D39 SVX3D Radiation Hardness test Rad test with Co 60 source up to 4MRad 55MeV proton beam to 15MRad Chip noise increases (30+3.2*Cap) electrons per Mrad Bare chip noise vs rad Cap dep. noise vs rad

40. 11 May 06UCSB Silicon Workshop: SVX3D40 Chip Problems: Wirebond Resonance Observed loss of data & power to Z sides of ladders Found to correlate with high trigger rates Failure due to wirebond resonances Wires orthogonal to magnetic field Wires feels Lorentz force during readout If frequency is right, wires resonate and break I  Wire Motion B More details in resonance talk!!

41. 11 May 06UCSB Silicon Workshop: SVX3D41 Chip Noise @ 8fb -1 Layer0 of SVX has chips with smallest radius from IP With init chip noise 1,600e and 18.3 pF load, the estimation is 5.5% noise increase per MRad Expect 17% of noise increase with 8fb -1 The S/N degradation will have large contribution by sensor shot noise. LayerChip R (cm) Expected dose Noise increase L00-132.4 Mrad13.5% L0(SVX)2.53.1 Mrad17% L1(SVX)4.11.4 Mrad8% Expectation at 8fb -1

42. 11 May 06UCSB Silicon Workshop: SVX3D42 How many chips SVX L0: 2 R & 2 Rz  4 Total L1: 3 R & 3 Rz  6 Total L2: 5 R & 5 Rz  10 Total L3: 6 R& 4 Rz  10 Total L4: 7 R & 7 Rz  14 Total ISL Each Ladder has 4(R) + 4(Rz) 8 chips Each DAQ Layer is 2 ladders 16 chips L00 Narrow: 1 chip Wide: 2 chips