1. Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design a chip as part of a system that accommodates the growing demand for radio frequency identification (RFID) technology while creating a quicker, more convenient shopping experience. Presentation #7: Smart Cart 525 Stage VIII: 16 Mar. 2005 Functional Blocks and Simulation

2. Status Design Proposal Project chosen Verilog obtained/modified Architecture Proposal Behavioral Verilog simulated Size estimates/floorplanning Gate-level implementation simulated in Verilog Floorplan and more accurate transistor count Schematic Design Component Layout Functional Block Layout (still working on encryption but most of it done) DRC of functional blocks LVS of functional blocks  Simulations (partially done)

3. Design Decisions Modification to floorplan  Not much except that the encryption block is more realistic and its components are coming together Adder/Multiplier  Since we used the small full adder with transmission gates, we had to buffer each full adder in the multiplier and adder Sbox  Simulations last week yielded we had to resize transistors and redo the ROM so we increased the size of our NMOS transistors

4. Old Floorplan: Entire Design

5. Old Top: Wiring Plan

6. New Floorplan: Reality v SRAM Adder

7. Floorplan Zoomed in Top

8. Sbox Logic Nice Layout

9. Sbox Logic Trouble

10. SRAM Simulations (Inputs/Outputs) Top 5 signals inputs and bottom 5 outputs

11. SRAM Simulations (Rise/Fall Times) Fall: 70.9587ps Rise: 126.563ps

12. Simulation Multiplier Too many outputs to be shown, and the signal does look good

13. Multiplier Simulations (Rise/Fall Times) Rise: 13.1ps Fall: 11.1977ps

14. New Buffered Adder

15. Adder Simulations (Rise/Fall Times) Fall: 13.55psRise: 19.434ps Propagation: 172.871ps

16. Key Expand with its Sbox Nice Layout

17. Sbox Simulations Before Buffering

18. Sbox Simulations After Buffering

19. Problems & Questions Wiring in encryption block  Turns out we need more space because of congestion around the top sbox logic and the other items close to it  We need to pass 128 bit wires, even if we use up every bit of space between the two SBOXes, it's still not enough! Logic and counters  Should be done but we want to do that last so it’s designed to fit the space we have for it therefore minimizing black space in the chip… good idea or bad idea