1. IC-UNICAMP MC 603/613 - 20061 - 1 Finite State Machines Mixed Style RTL Modeling Extraído da George Mason Univ. ECE 545 Lecture 5

2. IC-UNICAMP MC 603/613 - 20061 - 2 Finite State Machines (FSMs) Any Circuit with Memory Is a Finite State Machine –Even computers can be viewed as huge FSMs Design of FSMs Involves –Defining states –Defining transitions between states –Optimization / minimization Above Approach Is Practical for Small FSMs Only

3. IC-UNICAMP MC 603/613 - 20061 - 3 Máquina de Estados Circuito Sequencial Síncrono Genérico CC FF CC SiSi S i+1 X Y CC FF SiSi S i+1 X Y Máquina de MooreMáquina de Mealy Saída Y muda apenas na transição do clock Saída Y pode mudar em qualquer instante, em função da entrada X

4. IC-UNICAMP MC 603/613 - 20061 - 4 Síntese de uma máquina de estados S0S0 S1S1 S2S2 S3S3 Diagrama de Transição de Estados  Moore entr Mealy entr / saída Tabela de Transição de Estados

5. IC-UNICAMP MC 603/613 - 20061 - 5 Síntese de uma máquina de estados Codificação dos estados S 0 = 00 etc Equações booleanas dos circuitos combinacionais S i+1 = f S (S i, X) Y = f Y (S i, X) (em maq. de Moore, só S) Sintetizar os CCs Elementos de memória podem ser FF-D ou FF-JK

6. IC-UNICAMP MC 603/613 - 20061 - 6 Moore FSM Output Is a Function of Present State Only Present State Register Next State function Output function Inputs Present State Next State Outputs clock reset

7. IC-UNICAMP MC 603/613 - 20061 - 7 Mealy FSM Output Is a Function of a Present State and Inputs Next State function Output function Inputs Present State Next State Outputs Present State Register clock reset

8. IC-UNICAMP MC 603/613 - 20061 - 8 Moore Machine state 1 / output 1 state 2 / output 2 transition condition 1 transition condition 2

9. IC-UNICAMP MC 603/613 - 20061 - 9 Mealy Machine state 1 state 2 transition condition 1 / output 1 transition condition 2 / output 2

10. IC-UNICAMP MC 603/613 - 20061 - 10 Moore vs. Mealy FSM (1) Moore and Mealy FSMs Can Be Functionally Equivalent –Equivalent Mealy FSM can be derived from Moore FSM and vice versa Mealy FSM Has Richer Description and Usually Requires Smaller Number of States –Smaller circuit area

11. IC-UNICAMP MC 603/613 - 20061 - 11 Moore vs. Mealy FSM (2) Mealy FSM Computes Outputs as soon as Inputs Change –Mealy FSM responds one clock cycle sooner than equivalent Moore FSM Moore FSM Has No Combinational Path Between Inputs and Outputs –Moore FSM is more likely to have a shorter critical path

12. IC-UNICAMP MC 603/613 - 20061 - 12 Moore FSM - Example 1 Moore FSM that Recognizes Sequence “10” S0 / 0S1 / 0S2 / 1 0 0 0 1 1 1 reset Meaning of states: S0: No elements of the sequence observed S1: “1” observed S2: “10” observed

13. IC-UNICAMP MC 603/613 - 20061 - 13 Mealy FSM - Example 1 Mealy FSM that Recognizes Sequence “10” S0S1 0 / 0 1 / 0 0 / 1 reset Meaning of states: S0: No elements of the sequence observed S1: “1” observed

14. IC-UNICAMP MC 603/613 - 20061 - 14 Moore & Mealy FSMs – Example 1 clock input Moore Mealy 0 1 0 0 0 S0 S1 S2 S0 S0 S0 S1 S0 S0 S0

15. IC-UNICAMP MC 603/613 - 20061 - 15 FSMs in VHDL Finite State Machines Can Be Easily Described With Processes Synthesis Tools Understand FSM Description If Certain Rules Are Followed State transitions should be described in a process sensitive to clock and asynchronous reset signals only Outputs described as concurrent statements outside the process

16. IC-UNICAMP MC 603/613 - 20061 - 16 Moore FSM Present State Register Next State function Output function Inputs Present State Next State Outputs clock reset process(clock, reset) concurrent statements

17. IC-UNICAMP MC 603/613 - 20061 - 17 Mealy FSM Next State function Output function Inputs Present State Next State Outputs Present State Register clock reset process(clock, reset) concurrent statements

18. IC-UNICAMP MC 603/613 - 20061 - 18 FSM States (1) architecture behavior of FSM is type state is (list of states); signal FSM_state: state; begin process(clk, reset) begin if reset = ‘1’ then FSM_state <= initial state; elsif (clock = ‘1’ and clock’event) then case FSM_state is

19. IC-UNICAMP MC 603/613 - 20061 - 19 FSM States (2) case FSM_state is when state_1 => if transition condition 1 then FSM_state <= state_1; end if; when state_2 => if transition condition 2 then FSM_state <= state_2; end if; end case; end if; end process;

20. IC-UNICAMP MC 603/613 - 20061 - 20 Moore FSM - Example 1 Moore FSM that Recognizes Sequence “10” S0 / 0S1 / 0S2 / 1 0 0 0 1 1 1 reset

21. IC-UNICAMP MC 603/613 - 20061 - 21 Moore FSM in VHDL (1) TYPE state IS (S0, S1, S2); SIGNAL Moore_state: state; U_Moore: PROCESS (clock, reset) BEGIN IF(reset = ‘1’) THEN Moore_state <= S0; ELSIF (clock = ‘1’ AND clock’event) THEN CASE Moore_state IS WHEN S0 => IF input = ‘1’ THEN Moore_state <= S1; ELSE Moore_state <= S0; END IF;

22. IC-UNICAMP MC 603/613 - 20061 - 22 Moore FSM in VHDL (2) WHEN S1 => IF input = ‘0’ THEN Moore_state <= S2; ELSE Moore_state <= S1; END IF; WHEN S2 => IF input = ‘0’ THEN Moore_state <= S0; ELSE Moore_state <= S1; END IF; END CASE; END IF; END PROCESS; Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;

23. IC-UNICAMP MC 603/613 - 20061 - 23 Mealy FSM - Example 1 Mealy FSM that Recognizes Sequence “10” S0S1 0 / 0 1 / 0 0 / 1 reset

24. IC-UNICAMP MC 603/613 - 20061 - 24 Mealy FSM in VHDL (1) TYPE state IS (S0, S1); SIGNAL Mealy_state: state; U_Mealy: PROCESS(clock, reset) BEGIN IF(reset = ‘1’) THEN Mealy_state <= S0; ELSIF (clock = ‘1’ AND clock’event) THEN CASE Mealy_state IS WHEN S0 => IF input = ‘1’ THEN Mealy_state <= S1; ELSE Mealy_state <= S0; END IF;

25. IC-UNICAMP MC 603/613 - 20061 - 25 Mealy FSM in VHDL (2) WHEN S1 => IF input = ‘0’ THEN Mealy_state <= S0; ELSE Mealy_state <= S1; END IF; END CASE; END IF; END PROCESS; Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;

26. IC-UNICAMP MC 603/613 - 20061 - 26 Moore FSM – Example 2: State diagram Cz1=  resetn Bz0=  Az0=  w0= w1= w1= w0= w0= w1=

27. IC-UNICAMP MC 603/613 - 20061 - 27 Present Next state Output state w=0w=1 z AAB0 BAC0 CAC1 Moore FSM – Example 2: State table

28. IC-UNICAMP MC 603/613 - 20061 - 28 Moore FSM Present State Register Next State function Output function Input: w Present State: y Next State Output: z clock resetn process(clock, reset) concurrent statements

29. IC-UNICAMP MC 603/613 - 20061 - 29 USE ieee.std_logic_1164.all ; ENTITY simple IS PORT (clock : IN STD_LOGIC ; resetn : IN STD_LOGIC ; w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END simple ; ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN Moore FSM – Example 2: VHDL code (1)

30. IC-UNICAMP MC 603/613 - 20061 - 30 CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; WHEN C => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; END CASE ; Moore FSM – Example 2: VHDL code (2)

31. IC-UNICAMP MC 603/613 - 20061 - 31 Moore FSM – Example 2: VHDL code (3) END IF ; END PROCESS ; z <= '1' WHEN y = C ELSE '0' ; END Behavior ;

32. IC-UNICAMP MC 603/613 - 20061 - 32 Moore FSM Present State Register Next State function Output function Input: w Present State: y_present Next State: y_next Output: z clock resetn process (w, y_present) concurrent statements process (clock, resetn)

33. IC-UNICAMP MC 603/613 - 20061 - 33 ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y_present, y_next : State_type ; BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; WHEN B => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; Alternative VHDL code (1)

34. IC-UNICAMP MC 603/613 - 20061 - 34 WHEN C => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; END CASE ; END PROCESS ; PROCESS (clock, resetn) BEGIN IF resetn = '0' THEN y_present <= A ; ELSIF (clock'EVENT AND clock = '1') THEN y_present <= y_next ; END IF ; END PROCESS ; z <= '1' WHEN y_present = C ELSE '0' ; END Behavior ; Alternative VHDL code (2)

35. IC-UNICAMP MC 603/613 - 20061 - 35 A w0=z0=  w1=z1=  B w0=z0=  resetn w1=z0=  Mealy FSM – Example 2: State diagram

36. IC-UNICAMP MC 603/613 - 20061 - 36 Present Next stateOutput z state w=0w=1w=0w=1 AAB00 BAB01 Mealy FSM – Example 2: State table

37. IC-UNICAMP MC 603/613 - 20061 - 37 Mealy FSM Next State function Output function Input: w Present State: y Next State Output: z Present State Register clock resetn process(clock, reset) concurrent statements

38. IC-UNICAMP MC 603/613 - 20061 - 38 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Mealy IS PORT ( clock : IN STD_LOGIC ; resetn : IN STD_LOGIC ; w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END Mealy ; ARCHITECTURE Behavior OF Mealy IS TYPE State_type IS (A, B) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (clock'EVENT AND clock = '1') THEN Mealy FSM – Example 2: VHDL code (1)

39. IC-UNICAMP MC 603/613 - 20061 - 39 Mealy FSM – Example 2: VHDL code (2) CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; END CASE ;

40. IC-UNICAMP MC 603/613 - 20061 - 40 Mealy FSM – Example 2: VHDL code (3) END IF ; END PROCESS ; WITH y SELECT z <= w WHEN B, z <= ‘0’ WHEN others; END Behavior ;