1. Top 3mm (22 pads) x 6mm (59 pads) Vicm DAC_b DAC_p AVDD DAC_Iref DAC_Iout Iref Vicm AVDD AGND Vina Vinb DVDD DGND ClearB DFFclk1 DFFclk2 clkH1 clkH1_mod clkS1 clkS1_mod Set_bar1 Set_bar2 Dvalid_in Dvalid Dout Vref_p Vref_n XEN_SF_CALIB Comp_out_p Comp_out_n B Aout2 Aout1 AGND Xnew_clk_bar

2. clkS1 set_bar1 DFFclk1 clkH1 set_bar2 DFFclk2 sample_in (adc valid) Vina and Vinb are sampled here The ADC clock is clkS1 ORed with clkH1 The DIO Board is based on a 10MHz clock (0.1usec clock period) 1.2usec clock period 0.1u.2u.3u.4u.5u.6u.7u.8u.9u 1u 1.1u

3. clkS1 set_bar1 DFFclk1 clkH1 set_bar2 DFFclk2 sample_in (adc valid) Vina and Vinb are sampled here The ADC clock is clkS1 ORed with clkH1 The DIO Board is based on a 10MHz clock (0.1usec clock period) 1.2usec clock period 0.1u.2u.3u.4u.5u.6u.7u.8u.9u 1u 1.1u 1.2u One DAC Analog value Digital Control Signals

4. Din 1.2usec clock period 0 (1.2us) 2x(1.2us) 3x(1.2us) 4x(1.2us) 5x(1.2us) 6x(1.2us) DAC = 0 ADC Control Signals overview Digital Control Signals DAC = 1DAC = 2DAC = 3DAC = 4DAC = 5

5. Top

6. Design Number: 80172Customer Name: Brita Olson Design Name: CPP2_ADCCustomer Account: 3955 MOSIS PKG Name: PGA65Phone: (909) 869-2652 Quantity Packaged: AllFax: (909) 869-4687 Min Pad Size (X): 78umMin Pad pitch (X): 90 um Min Pad Size (Y): 78umMin Pad pitch (Y): 90 um Cavity size: 400milsNo Rotation