1. 1 Enhancing Random Access Scan for Soft Error Tolerance Fan Wang* Vishwani D. Agrawal Department of Electrical and Computer Engineering, Auburn University, AL 36849 *Now with Juniper Networks, Inc. Sunnyvale, CA, 94086 42 nd IEEE Southeastern Symposium on System Theory, March, 2010

2. 2 Motivation for This Work Recent work on random access scan (RAS) has shown its advantages in reducing test time, test volume and test power over serial scan (SS). The RAS structure can also improve the fault tolerance ability in both normal function mode and test mode.

3. 3 Outline Background Review of RAS design Soft error tolerance of RAS A new scan-out structure Further enhancing error tolerance using RAS structure Conclusion

4. 4 Soft Errors Soft errors are caused by the operating environment. They are not due to permanent hardware faults. Soft errors are intermittent or random, which makes their testing unreliable. One way to deal with soft errors is to make hardware robust: –Capable of detecting soft errors –Capable of correcting soft errors –Both measures are probabilistic

5. 5 Effect on Digital Circuit INOUT CK Combinational Logic Charged Particles Charged Particles M. Nicolaidis (Editor), Soft Errors in Modern Electronic Systems, Springer, 2010. Flip-flops

6. 6 Random Access Scan (RAS) Testing requires that flip-flops be controllable and observable. Two methods are: –Serial scan (SS) using shift register –Random access scan (RAS) using memory-like addressing RAS reduces test application time and test power, which are otherwise complementary objectives in SS. Previous and current publications on RAS: Ando, COMPCON -80 Wagner, COMPCON -83 Ito, DAC -90 Bushnell & Agrawal, textbook, pp. 484-485 Mudlapur et al., ITC -05 Saluja et al., VLSI Design -04, ITC -05, ATS -05, VLSI Design -06, VLSI Design -10.

7. 7 Background Error tolerant computing techniques are characterized by the level of reliability: 1.Device level error tolerance techniques either increase the device critical charge or decrease the collected charge to reduce SER 2.Circuit or system level error tolerance techniques include error detection and correction (EDAC) codes and time/space redundancy.

8. 8 BISER Design With C-Element S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. S. Kim, “Robust System Design with Built-In Soft-Error Resilience,” Computer, vol. 38, no. 2, pp. 43-52, February 2005.

9. 9 The “Toggle” RAS Flip-Flop MS Clock MUXMUX Combinational Logic Data Row Decoder Column Decoder Combinational Logic Data Logic Data To Output BUS Address (log 2 n ff ) y x √n ff Lines RAS-FF 0 1 OutputBUSControl

10. Natural Soft Error Tolerance of RAS 10 For SS, soft error can be induced on each SFF as it transports test data to output. For RAS, only when selected RAS cell has induced error, will the result be affected.

11. SER Analysis 11 For a 4- cell RAS structure, the SER is N · ( A + Δ)· P · α f For a 4-cell SS structure, the SER is 4N · A · P · α f Where N is the particle flux in #particles · cm -2 · s -1 A is sensitive area per FF in cm 2 P is probability of SET per strike in a FF Δ is average area overhead (routing, decoder, etc.) per FF to implement RAS αf is a temporal derating factor between 0 and 1

12. 12 Fault Tolerant Design Using BISER-RAS x1 y1y2y3y4 RAS FF11 RAS FF14 RAS FF12 RAS FF13 RAS To Next Level Copy R1 R11R12R13 ck C- x2 RAS FF11 RAS FF14 RAS FF12 RAS FF13 RAS C- x3 FF11 RAS FF14 RAS FF12 RAS FF13 RAS C- Copy R2 R21R22R23 Copy R3 R31R32R33

13. Hardware overheads comparison for ISCAS’89 Circuit 13 Ckt#FF #Gate BISER design overhead (%) TMR design overhead (%) SSRASReductionSSRASReduction s208811287.4182.415.09283.3397.14186.19 S3491117680.7771.679.10261.5483.26178.28 s510621146.4946.450.04150.5555.4995.06 s11961852953.3143.639.68172.6449.61123.02 s1494 664717.8217.810.0257.7121.2736.44 s5378179277982.2753.4528.82266.4056.38210.02 s9234221559757.4937.0020.49186.1738.88147.28 s13207 638795193.4957.3036.19302.7359.06243.67 s15850 534977274.2145.7728.44240.2947.30192.99 s35932 17281606508.83164.9343.90352.3966.18286.21 s38417 16362217989.1553.2535.90288.6654.30234.36 s38584 14261925389.3653.5435.82289.3454.67234.68 Average73.1452.1420.51 236.8357.55179.28

14. 14 Conclusion The RAS design has a natural soft error tolerance capability that is inherited from its unique structural and operation. In a circuit with N FFs, the SER of RAS can be nearly 1/N that for the SER of SS. The BISER-RAS can save on average 20.51% hardware over BISER applied to SS, and TMR-RAS saves on average of 179.28% over TMR-SS for ISCAS89 benchmarks.