1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 313 - Computer Organization Lecture 7 - Introduction to Verilog Fall 2004 Reading: B.4, Verilog Handout Sections 1-4, 5.1 Note: “For More Practice” problems are on the CDROM Portions of these slides are derived from: Textbook figures © 1998 Morgan Kaufmann Publishers all rights reserved Tod Amon's COD2e Slides © 1998 Morgan Kaufmann Publishers all rights reserved Dave Patterson’s CS 152 Slides - Fall 1997 © UCB Rob Rutenbar’s 18-347 Slides - Fall 1999 CMU other sources as noted

2. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog2 Outline - Introduction to Verilog  Goals of HDL-Based Design  A First Example  Module and Port Declarations  Modeling with Continuous Assignments  Some Language Details  Modeling with Hierarchy  Modeling with always blocks (combinational logic)  Demonstration: Using Verilogger  Discuss Project 1  Summary

3. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog3 Goals of HDL-Based Design  Model hardware for  Simulation - predict how hardware will behave  Synthesis - generate optimized hardware  Provide a concise text description of circuits  Support design of very large systems

4. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog4 A First Example  Full Adder from Lecture 6: module fulladder(a, b, cin, sum, cout); input a, b, cin; output sum, cout; assign sum = a ^ b ^ cin; assign cout = a & b | a & cin | b & cin; endmodule Ports Port Declarations Semicolon NO Semicolon Continuous Assignment Statements

5. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog5 Comments about the First Example  Verilog describes a circuit as a set of modules  Each module has input and output ports  Single bit  Multiple bit - array syntax  Each port can take on a digital value (0, 1, X, Z)  Three main ways to specify module internals  Continuous assignment statements - assign  Concurrent statements - always  Submodule instantiation (hierarchy)

6. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog6 Bitwise Operators  Basic bitwise operators: identical to C/C++/Java module inv(a, y); input[3:0]a; output [3:0]y; assign y = ~a; endmodule Unary Operator: NOT 4-bit Ports

7. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog7 Reduction Operators  Apply a single logic function to multiple-bit inputs module and8(a, y); input[7:0]a; output y; assign y = &a; endmodule Reduction Operator: AND equivalent to: a[7] & a[6] & a[5] & a[4] & a[3] & a[2] & a[2] & a[2] & a[0]

8. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog8 Conditional Operators  Like C/C++/Java Conditional Operator module mux2(d0, d1, s, y); input[3:0]d0, d1; inputs; output [3:0]y; assign y = s ? d1 : d0; // output d1 when s=1, else d0 endmodule Comment

9. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog9 More Operators  Equivalent to C/C++/Java Operators  Arithmetic: + - * / &  Comparison: == != >=  Shifting: >  Example: module adder(a, b, y); input[31:0]a, b; output[31:0]y; assign y = a + b; endmodule  Warning: small expressions can make big hardware if complex operators are used!

10. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog10 Bit Manipulation: Concatenation  { } is the concatenation operator module adder(a, b, y, cout); input[31:0]a, b; output[31:0]y; output cout; assign {cout,y} = a + b; endmodule Concatenation (33 bits)

11. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog11 Bit Manipulation: Replication  { n {pattern} } replicates a pattern n times module signextend(a, y); input[15:0]a; output [31:0]y; assign y = {16{a[15]}, a[15:0]}; endmodule Copies sign bit 16 times Lower 16 Bits

12. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog12 Internal Signals  Declared using the wire keyword module fulladder(a, b, cin, s, cout); inputa, b, cin; output s, cout; wireprop; assign prop = a ^ b; assign s = prop ^ cin; assign cout = (a & b) | (cin & (a | b)); endmodule Important point: these statements “execute” in parallel

13. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog13 Some Language Details  Syntax - See Quick Reference Card  Major elements of language:  Lexical Elements (“tokens” and “token separators”)  Data Types and Values  Operators and Precedence

14. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog14 Verilog Lexical Elements  Whitespace - ignored except as token separators  blank spaces  tabs  newlines  Comments  Single-line comments //  Multi-line comments /* … */  Operators- unary, binary, ternary  Unary a = ~b;  Binary a = b && c;  Ternary a = (b < c) ? b : c;

15. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog15 Verilog Numbers  Sized numbers: '  - decimal number specifying number of bits  - base of number decimal 'd or 'D hex 'h or 'H binary ‘b or ‘B  - consecutive digits normal digits 0, 1, …, 9 (if appropriate for base) hex digitsa, b, c, d, e, f x "unknown" digit z "high-impedance" digit  Examples 4’b111112’h7af16’d255

16. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog16 Verilog Numbers (cont'd)  Unsized numbers  Decimal numbers appearing as constants (236, 5, 15, etc.)  Bitwidth is simulator-dependent (usually 32 bits)  Negative numbers  sized numbers: '-' before size -8'd127 -3'b111  unsized numbers: '-' before first digit -233  Underline '_' can be used as a "spacer” 12'b00010_1010_011 is same as 12'b000101010011

17. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog17 Verilog Strings  Anything in quotes is a string: "This is a string" "a / b"  Strings must be on a single line  Treated as a sequence of 1-byte ASCII values  Special characters - C-like (\)

18. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog18 Verilog Identifiers  Starting character: alphabetic or '_'  Following characters: alpha, numeric, or '_'  Examples: george_paul  "Escaped" identifiers:  start with backslash  follow with any non-whitespace ASCII  end with whitespace character  Examples: \212net\**xyzzy**\$foo  Special notes:  Identifiers are case sensitive  Identifiers may not be reserved words

19. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog19 Verilog Reserved Words alwaysandassignbeginbufbufif0bufif1 case casexcasezcmos deassigndefaultdefparamdisableedge elseendendcaseendfunctionendmodule endprimitiveendspecifyendtableendtaskeventfor forceforeverforkfunctionhighz0highz1ififnone initialinoutinputintegerjoinlargemacromodule mediummodulenandnegedgenmosnor not notif0notiforoutputparameterpmos posedgeprimitivepull0pull1pulldownpulluprcmos realrealtimeregreleaserepeatrnmosrpmosrtran rtranif0rtranif1scalaredsmallspecifyspecparamstrong0 strong1supply0supply1tabletasktimetrantranif0 tranif1tritri0tri1triandtriortriregvectored waitwandweak0weak1whilewireworxnor xor

20. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog20 Verilog Data Types  Nets - connections between modules  input, output ports  wires - internal signals  Other types: wand, wor, trior, trireg (ignore for now)  Advanced Data Types (more later)  Vectors - multiple bit wires, registers, etc.  reg - Variables that are assigned values  Arrays and Memories  Parameters

21. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog21 Operators and Precedence  Override with parentheses () when needed

22. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog22 Modeling with Hierarchy  Create instances of submodules  Example: Create a 4-input Mux using mux2 module  Original mux2 module: module mux2(d0, d1, s, y); input[3:0]d0, d1; inputs; output [3:0]y; assign y = s ? d1 : d0; endmodule

23. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog23 Modeling with Hierarchy  Create instances of submodules  Example: Create a 4-input Mux using mux2 module module mux4(d0, d1, d2, d3, s, y); input[3:0]d0, d1, d2, d3; input[1:0]s; output [3:0]y; wire[3:0]low, high; mux2 lowmux(d0, d1, s[0], low); mux2 highmux(d2, d3, s[0], high); mux2 finalmux(low, high, s[1], y); endmodule Instance NamesConnections

24. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog24 Larger Hierarchy Example  Use full adder to create an n-bit adder module add8(a, b, sum, cout); input [7:0] a, b; output [7:0] sum; output cout; wire [7:0] c; // used for carry connections assign c[0]=0; fulladder f0(a[0], b[0], c[0], sum[0], c[1]); fulladder f1(a[1], b[1], c[1], sum[1], c[2]); fulladder f2(a[2], b[2], c[2], sum[2], c[3]); fulladder f3(a[3], b[3], c[3], sum[3], c[4]); fulladder f4(a[4], b[4], c[4], sum[4], c[5]); fulladder f5(a[5], b[5], c[5], sum[5], c[6]); fulladder f6(a[6], b[6], c[6], sum[6], c[7]); fulladder f7(a[7], b[7], c[7], sum[7], cout); endmodule

25. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog25 Hierarchical Design with Gate Primitives  “Built-In” standard logic gates and or not xor nand nor xnor  Using Gate Primitives: and g1(y, a, b, c, d);  How are the different from operators ( &, |, ~, etc.)?  Operators specify function  Gate primitives specify structure Output Inputs (variable number)

26. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog26 Gate Primitives Example  2-1 Multiplexer module mux2s(d0, d1, s, y); wire sbar, y0, y1; not inv1(sbar, s); and and1(y0, d0, sbar); and and2(y1, d1, s); or or1(y, y0, y1); endmodule;  Why shouldn’t we use gate primitives?  Requires “low-level” implementation decisions  It’s often better to let synthesis tools make these

27. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog27 Procedural Modeling with always  Motivation  assign statements are fine for simple functions  More complex functions require procedural modeling  Basic syntax: always @(sensitivity-list) statement or always @(sensitivity-list) begin statement-sequence end Signal list - change activates block Procedural statement ( =, if/else, etc.) Compound Statement - sequence of procedural statements

28. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog28 Combinational Modeling with always  Example: 4-input mux behavioral model module mux4(d0, d1, d2, d3, s, y); input d0, d1, d2, d3; input [1:0] s; output y; reg y; always @(d0 or d1 or d2 or d3 or s) case (s) 2'd0 : y = d0; 2'd1 : y = d1; 2'd2 : y = d2; 2'd3 : y = d3; default : y = 1'bx; endcase endmodule

29. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog29 Demonstration: Using Verilogger  Starting Verilogger  Start->Program Files->Synapticad->Verilogger Pro  Key Windows:  Project Manager  HDL Editor Windows  Timing Diagram Window  Creating and Simulating a Verilog file  Editor->New HDL File  Editor->Save HDL File As...  Project->Add File to Project  Simulate->Build (yellow button)  Simulate->Run (green “play” button)

30. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog30 Assignment - Project 1  Modeling and Simulating Arithmetic Circuits  Part 1 Basic Ripple Adder - expand 8 bit to 16 bit Carry Lookahead Adder Simulate with several different values to exercise fully Add delays and re-simulate Hand in listings, annotated simulation timing diagrams  Part 2 Basic ALU Slice 16-bit ALU (note no carry in) 16-bit ALU with Carry Lookahead Simulate with several different values to exercise fully Add delays and re-simulate Hand in listings, annotated simulation timing diagrams

31. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog31 Review - ALU Slice  Bit i

32. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog32 Review - ALU Structure  16 bit

33. ECE 313 Fall 2004Lecture 7 - Introduction to Verilog33 Coming Up  Multiplication and Division  Floating Point