1. Week 3 Presentation Kevin Cheung Michael Glowacki Alex Romine Dave Sexton

2. Opcodes register-register instructions(R-type)OPCODEFUNCT sll = r,0x04000000000100 srl = r,0x06000000000110 sra = r,0x07000000000111 add = r,0x20000000100000 addu= r,0x21000000100001 sub = r,0x22000000100010 subu= r,0x23000000100011 and = r,0x24000000100100 or = r,0x25000000100101 xor = r,0x26000000100110 seq = r,0x28000000101000 sne = r,0x29000000101001 slt = r,0x2a000000101010 sgt = r,0x2b000000101011 sle = r,0x2c000000101100 sge = r,0x2d000000101101 movi2s = r,0x30000000110000 movs2i = r,0x31000000110001 movf = r,0x32000000110010 movd = r,0x33000000110011 movfp2i = r,0x34000000110100 movi2fp = r,0x35000000110101 movi2t = r,0x36000000110110 movi2i = r,0x37000000110111 sltu = r,0x3a000000111010 sgtu = r,0x3b000000111011 sleu = r,0x3c000000111100 sgeu = r,0x3d000000111101

3. Opcodes – cont. floating-point instructions (R-type) addf = f,0x00000001000000 subf = f,0x01000001000001 multf = f,0x02000001000010 divf = f,0x03000001000011 addd = f,0x04000001000100 subd = f,0x05000001000101 multd = f,0x06000001000110 divd = f,0x07000001000111 cvtf2d = f,0x08000001001000 cvtf2i = f,0x09000001001001 cvtd2f = f,0x0a000001001010 cvtd2i = f,0x0b000001001011 cvti2f = f,0x0c000001001100 cvti2d = f,0x0d000001001101 mult = f,0x0e000001001110 div = f,0x0f000001001111 eqf = f2,0x10000001010000 nef = f2,0x11000001010001 ltf = f2,0x12000001010010 gtf = f2,0x13000001010011 lef = f2,0x14000001010100 gef = f2,0x15000001010101 multu = f,0x16000001010110 divu = f,0x17000001010111 eqd = f2,0x18000001011000 ned = f2,0x19000001011001 ltd = f2,0x1a000001011010 gtd = f2,0x1b000001011011 led = f2,0x1c000001011100 ged = f2,0x1d000001011101

4. Opcodes – cont. general instructionOPCODE j= j,0x02J000010 jal= j,0x03J000011 beqz= b,0x04I000100 bnez= b,0x05I000101 bfpt= b0,0x06I000110 bfpf= b0,0x07I000111 addi= i,0x08I001000 addui= i,0x09I001001 subi= i,0x0aI001010 subui= i,0x0bI001011 andi= i,0x0cI001100 ori= i,0x0dI001101 xori= i,0x0eI001110 lhi= i1,0x0fI001111 rfe= n,0x10J010000 trap= t,0x11J010001 jr= jr,0x12I010010 jalr= jr,0x13I010011 slli= i,0x14I010100 nop= n,0x15R010101 srli= i,0x16I010110 srai= i,0x17I010111 seqi= i,0x18I011000 OPCODE snei= i,0x19I011001n/a slti= i,0x1aI011010n/a sgti= i,0x1bI011011n/a slei= i,0x1cI011100n/a sgei= i,0x1dI011101n/a lb= l,0x20I100000n/a lh= l,0x21I100001n/a lw= l,0x23I100011n/a lbu= l,0x24I100100n/a lhu= l,0x25I100101n/a lf= l,0x26I100110n/a ld= l,0x27I100111n/a sb= s,0x28I101000n/a sh= s,0x29I101001n/a sw= s,0x2bI101011n/a sf= s,0x2eI101110n/a sd= s,0x2fI101111n/a sltui= s,0x3aI111010n/a sgtui= s,0x3bI111011n/a sleui= s,0x3cI111100n/a sgeui= s,0x3dI111101n/a

5. Zero Extender

6. Zero Extender - Trace

7. SRL Shifter

8. SRL Shifter - Trace

9. SRA Shifter

10. SRA Shifter - Trace

11. Register File

12. Register File – Trace

13. 1 Bit ALU – Implemented XOR

14. 1 Bit ALU Trace

15. 32 Bit ALU

16. 32 Bit ALU - Trace

17. Week 4Week 5Week 6 1/27/08 - 2/2/082/3/08 - 2/9/082/10/08 - 2/16/08 Add Registers Between Steps Plan layout of entire processor Control Signals Hazards MULT Loads Stores Moves Set Conditionals Branches Jumps Trap/RFE

18. Plan Layout of Processor

19. Control Signals Implement a PLA that interprets the opcode of the DLX processor. Implement a PLA that interprets the opcode of the DLX processor. Need to decide what control signals we will need and what they will be for each instruction. Need to decide what control signals we will need and what they will be for each instruction.

20. Hazards Data Data Detection: Test if destination register of previous instructions are the same as the source register of the current instruction. Detection: Test if destination register of previous instructions are the same as the source register of the current instruction. Handling: Forward the data from the previous instruction. Handling: Forward the data from the previous instruction.

21. Hazards Structural Structural Detection: Happens if 2 registers would need to write a register at the same time. Detection: Happens if 2 registers would need to write a register at the same time. Handling: Insert a stall Handling: Insert a stall

22. Hazards Control Control Detection: Any conditional branch Detection: Any conditional branch Handling: Stall the pipeline until the branch result is known. Handling: Stall the pipeline until the branch result is known.