1. Center for Embedded Computer Systems University of California, Irvine and San Diego http://www.cecs.uci.edu/~spark SPARK: A Parallelizing High-Level Synthesis Framework Supported by Semiconductor Research Corporation & Intel Inc Sumit Gupta Rajesh Gupta, Nikil Dutt, Alex Nicolau

2. 2 System Level Synthesis System Level Model Task Analysis HW/SW Partitioning ASIC Processor Core Memory FPGA I/O Hardware Behavioral Description Software Behavioral Description Software Compiler High Level Synthesis

3. 3 High Level Synthesis M e m o r y ALU Control Data path d = e - fg = h + i If Node TF c x = a + b c = a < b j = d x g l = e + x x = a + b; c = a < b; if (c) then d = e – f; else g = h + i; j = d x g; l = e + x; Transform behavioral descriptions to RTL/gate level From C to CDFG to Architecture

4. 4 Our Approach: Parallelizing HLS (PHLS) C Input VHDL Output Original CDFG Optimized CDFG Scheduling & Binding Source-Level Compiler Transformations Scheduling Compiler & Dynamic Transformations Optimizing Compiler and Parallelizing Compiler transformations applied at Source-level (Pre-synthesis) and during Scheduling Optimizing Compiler and Parallelizing Compiler transformations applied at Source-level (Pre-synthesis) and during Scheduling Source-level code refinement using Pre-synthesis transformations Source-level code refinement using Pre-synthesis transformations Code Restructuring by Speculative Code Motions Code Restructuring by Speculative Code Motions Operation replication to improve concurrency Operation replication to improve concurrency Dynamic transformations: exploit new opportunities during scheduling Dynamic transformations: exploit new opportunities during scheduling

5. 5 Speculative Code Motions + + If Node TF Reverse Speculation Conditional Speculation Across Hierarchical Blocks _ a b c Operation Movement to reduce impact of Programming Style on Quality of HLS Results Early Condition Execution Evaluates conditions As soon as possible

6. 6 Dynamic Branch Balancing If Node TF _ e BB 0 BB 2 BB 1 BB 3 BB 4 + a + b _ c _ d S0 S1 S2 S3 + Resource Allocation Original Design If Node TF _ e BB 0 BB 2 BB 1 BB 3 BB 4 + a + b _ c _ d Scheduled Design Unbalanced Conditional

7. 7 Insert New Scheduling Step in Shorter Branch If Node TF BB 0 BB 2 BB 1 BB 3 BB 4 + a + b _ c _ d If Node TF _ e BB 0 BB 2 BB 1 BB 3 BB 4 + a + b _ c _ d S0 S1 S2 S3 + Resource Allocation e __ e Original DesignScheduled Design

8. 8 New Opportunities for “Dynamic” CSE Due to Code Motions BB 2BB 3 BB 1 a = b + c BB 6BB 7 BB 5 d = b + c BB 4 BB 8 Scheduler decides to Speculate BB 2BB 3 BB 1 a = dcse BB 6BB 7 BB 5 d = dcse BB 4 BB 8 dcse = b + c BB 0 CSE not possible since BB2 does not dominate BB6 CSE possible now since BB0 does not dominate BB6

9. 9 Loop Shifting: An Incremental Loop Pipelining Technique BB 0 a + b c _ + _ d Loop Exit Loop Node BB 3 BB 2 BB 1 BB 4 BB 0 b + _ d Loop Exit Loop Node BB 3 BB 2 BB 1 BB 4 a + c _ a + c _ After Loop Shifting BB 0 b + _ d Loop Exit Loop Node BB 3 BB 2 BB 1 BB 4 a + c _ a + c _ Compaction Original Design

10. 10 SPARK High Level Synthesis Framework

11. 11 SPARK Parallelizing HLS Framework C input and Synthesizable RTL VHDL output C input and Synthesizable RTL VHDL output Tool-box of Transformations and Heuristics Tool-box of Transformations and Heuristics Each of these can be developed independently of the other Each of these can be developed independently of the other Script based control over transformations & heuristics Script based control over transformations & heuristics Hierarchical Intermediate Representation (HTGs) Hierarchical Intermediate Representation (HTGs) Retains structural information about design (conditional blocks, loops) Retains structural information about design (conditional blocks, loops) Enables efficient and structured application of transformations Enables efficient and structured application of transformations Complete HLS tool: Does Binding, Control Synthesis and Backend VHDL generation Complete HLS tool: Does Binding, Control Synthesis and Backend VHDL generation Interconnect Minimizing Resource Binding Interconnect Minimizing Resource Binding Enables Graphical Visualization of Design description and intermediate results Enables Graphical Visualization of Design description and intermediate results 100,000+ lines of C++ code 100,000+ lines of C++ code

12. 12 Synthesizable C ANSI-C front end from Edison Design Group (EDG) ANSI-C front end from Edison Design Group (EDG) Features of C not supported for synthesis Features of C not supported for synthesis Pointers Pointers However, Arrays and passing by reference are supported However, Arrays and passing by reference are supported Recursive Function Calls Recursive Function Calls Gotos Gotos Features for which support has not been implemented Features for which support has not been implemented Multi-dimensional arrays Multi-dimensional arrays Structs Structs Continue, Breaks Continue, Breaks Hardware component generated for each function Hardware component generated for each function A called function is instantiated as a hardware component in calling function A called function is instantiated as a hardware component in calling function

13. 13 + Speculative Code Motions + Pre-Synthesis Transforms + Dynamic CSE Scheduling & Logic Synthesis Results Non-speculative CMs: Within BBs & Across Hier Blocks 42% 10% 36% 8% 39%

14. 14 Non-speculative CMs: Within BBs & Across Hier Blocks + Speculative Code Motions + Pre-Synthesis Transforms + Dynamic CSE Scheduling & Logic Synthesis Results 14% 20% 1% 33% 41% 52%

15. 15 Case Study: Intel Instruction Length Decoder Speculate Operations, Fully Unroll Loop, Eliminate Loop Index Variable Multi-cycle Sequential Architecture Multi-cycle Sequential Architecture Single cycle Parallel Architecture Single cycle Parallel Architecture

16. SPARK: A Parallelizing

17. High-Level Synthesis

18. Framework

19. Center for Embedded Computer Systems University of California, Irvine and San Diego http://www.cecs.uci.edu/~spark SPARK: A Parallelizing High-Level Synthesis Framework Supported by Semiconductor Research Corporation & Intel Inc Sumit Gupta, Rajesh Gupta, Nikil Dutt, Alex Nicolau