1. 5 Top PED/Robustness Roadmapping Needs 1.Power and energy reduction achievable with less intrusive and more evolutionary techniques  Ex: dual-Vdd incurs a lot of physical design headaches as well as great reliance on level conversion and algorithms to assign Vdds  Alternatively, can a single Vdd, many Vth process/approach achieve 20%, 50%, or 90% of the gains that dual-Vdd does? 2.Area/power overhead to create robust design  Ex: techniques that use redundancy, error checking, lead to area and power overhead but become increasingly necessary  How much redundancy and other error-checking hardware is needed and when?

2. 5 Top PED/Robustness Roadmapping Needs, cont. 3.Prioritize between low-power design techniques and parametric yield/reliability  Critical path density skyrockets as low power design techniques are leveraged  Timing closure becomes even more difficult  Better to back off a little to balance power and yield  Quantify this – plot at right is a first cut 4.Variability in leakage (both subthreshold and gate)  How bad is it?  Exponentially dependent on Vth, Tox, etc. BUT averaging effects may help us  Skewed lognormal distributions of leakage imply that a handful of gates consume a disproportionate share of total leakage  Design techniques to address: adaptive body bias to combat process variation on a chip-by-chip basis (Intel)  When will high-k gate dielectrics really save us on Igate and how will they proliferate within the industry? 5.Optimal leakage/dynamic power breakdown during normal operation (not standby modes)  30% has been proposed  When will this be exceeded in typical designs and what techniques are available to put this day off while still meeting performance requirements?

3. Algorithms, Optimization, Modeling How to take advantage of techniques that are being proposed?  Need approaches to simultaneous Vdd/Vth assignment with sizing  Statistical timing analysis should be integrated within low-power tools to concurrently model their impact on parametric yield (this will take a while…)  Final power sign-off is critical: considers temperature gradients, power supply fluctuations, Monte Carlo type analysis for variability (very slow, alternatives?)  Design space exploration tools become more critical as the number of variables increase Ex. 5 Vth’s, 3 Tox’s, a continuous range of Vdd’s, liquid libraries  Non-power content: Is it possible to manipulate design rules to: 1) improve yield and minimize impact on performance and 2) reduce costs through lessened need for OPC and other lithographic correction techniques