1. Microelectronic Circuits - Fourth Edition Sedra/Smith 0 Fig. 14.1 Switching times of the BJT in the simple inverter circuit of (a) when the input v 1 has the pulse waveform on (b). The effects of stored base charge following the return of v 1 to V 1 are explained in conjunction with Eqs. (14.2) and (14.3).

2. Microelectronic Circuits - Fourth Edition Sedra/Smith 1 Fig. 14.20 Analysis of the TTL gate with the input high. The circled numbers indicate the order of the analysis steps.

3. Microelectronic Circuits - Fourth Edition Sedra/Smith 2 Fig. 14.22 Analysis of the TTL gate when the input is low. The circled numbers indicate the order of the analysis steps.

4. Microelectronic Circuits - Fourth Edition Sedra/Smith 3 Fig. 14.23 The TTL gate and its voltage transfer characteristic.

5. Microelectronic Circuits - Fourth Edition Sedra/Smith 4 Fig. 14.24 The TTL NAND gate.

6. Microelectronic Circuits - Fourth Edition Sedra/Smith 5 Fig. 14.25 Structure of the multiemitter transistor Q 1.

7. Microelectronic Circuits - Fourth Edition Sedra/Smith 6 Fig. 14.28 A Schottky TTL (known as STTL) NAND gate.

8. Microelectronic Circuits - Fourth Edition Sedra/Smith 7 Fig. 14.33 Basic gate circuit of the ECL 10K family.

9. Microelectronic Circuits - Fourth Edition Sedra/Smith 8 Fig. 14.35 Simplified version of the ECL gate for the purpose of finding transfer characteristics.

10. Microelectronic Circuits - Fourth Edition Sedra/Smith 9 Fig. 14.36 The OR transfer characteristic v OR versus v 1, for the circuit in Fig. 14.35.

11. Microelectronic Circuits - Fourth Edition Sedra/Smith 10 Fig. 14.38 The NOR transfer characteristic, v NOR versus v 1, for the circuit in Fig. 14.35.

12. Microelectronic Circuits - Fourth Edition Sedra/Smith 11 Fig. 14.44 Development of the BiCMOS inverter circuit: (a) The basic concept is to use an additional bipolar transistor to increase the output current drive of each Q N and Q P of the CMOS inverter; (b) the circuit in (a) can be thought of as utilizing these composite devices; (c) to reduce the turn-off times of Q 1 and Q 2, “bleeder resistors” R 1 and R 2 are added; (d) implementation of the circuit in (e) using NMOS transistors to realize the resistors; (e) an improved version of the circuit in (c) obtained the lower end of R 1 to the output mode.