1. ENEE 644 Dr. Ankur Srivastava Office: 1349 A.V. Williams Email: ankurs@eng.umd.edu URL: http://www.ece.umd.edu/class/enee644/ Computer-Aided Design of Digital Systems -- Logic Synthesis and Optimization

2. ENEE 6442 Course Outline > Introduction > Algorithms and Tools > Two-Level Logic Synthesis > Multi-Level Logic Synthesis > Sequential System Synthesis

3. ENEE 6443 Introduction > Very Large Scale Integration (VLSI) > Computer-Aided Design > Design Process > Design Styles > Logic Synthesis: an Overview > Design Space and Optimization

4. ENEE 6444 > Integrated Circuits =SSI, MSI, LSI, and VLSI =Moore’s Law > Microelectronics is the Enabling Technology (Micro-Electro-Mechanics more recently) > Design Automation is the Enabling Tool VLSI Circuits

5. ENEE 6445 Moore’s Law > The logic density of silicon integrated circuits is doubled every 18 months.

6. ENEE 6446 Intel 4004 (1971) > Intel’s first microprocessor > 2,300 transistors > 108 KHz > 10 micron

7. ENEE 6447 Intel386™ (1985) > First 32-bit chip > 275,000 transistors > 16MHz – 33 MHz > 1 micron > Multi-tasking

8. ENEE 6448 Pentium ® III(1999) > 9.5 million transistors > 0.25-micron technology > Internet Streaming SIMD extensions

9. ENEE 6449 Design Technology Challenges > Productivity design meaningfully with huge number of transistors > Power design under the single-chip package power limit design under the single-chip package power limit > Manufacturing Integration > Interference resource-efficient communication and synchronization > Error-Tolerance relaxation of the requirement of 100% correctness Source: ITRS 2001 Edition

10. ENEE 64410 Computer Aided Design > Role > History > Difficulty: size, NP-hard > Market and Key Players =Tens of billions $ industry =4 major CAD companies =CAD groups in large companies =Universities with strong CAD groups > Conferences and Journals

11. ENEE 64411 Brief History of CAD > 1950-1965 manual design, impractical algorithms (even for MSI). > 1965-1975 physical design tools for automatic layout of gate arrays IBM: Engineering Design System AT&T: LTX system for standard cells logic design tools: IBM’s Mini: 2-level heuristic minimizer Espresso: (IBM and Berkeley) PLA-based design > 1975-1985 placement and routing, technology mapping, multi-level optimization theoretical development in physical design > 1985- performance/power driven design methodologies parallel algorithm, graph theory, combinatorial optimization problems

12. ENEE 64412 Design Process > System Specification > Functional Design > Logic Design > Circuit Design > Physical Design > Fabrication > Packaging

13. ENEE 64413 Design Styles > Full Custom > Semi-Custom > Programmable > Trade-off: Cost, flexibility, performance, area, power, time-to- market

14. ENEE 64414 Logic Synthesis: Overview > Goals: =Generate the logic-level model of the system =Optimize the logic-level model > Problems and Tools: =Two-level circuits: Boolean algebra, Binary decision diagram =Multi-level circuits: Boolean networks, Factored form =Sequential circuits: Finite state machine, graph algorithms

15. ENEE 64415 Design Space and Optimality > Implement a circuit that outputs true iff all four inputs are true using 2- and 3-input AND gates. =Logic specification. =How many different implementations? =Area and delay: optimization targets. =Trade-off curve and Pareto points.

16. ENEE 64416 Design Space and Optimality (cont’d) area delay area constraint delay constraint Trade-off curve Set of Pareto points Optimal designs failed design successful design optimal design X infeasible design optimization