1. March 2005 1R. Smith - University of St Thomas - Minnesota ENGR 330: Today’s Class Toys, er, Processor TechnologyToys, er, Processor Technology Cache ReviewCache Review Magic: fully associative cacheMagic: fully associative cache Four Questions/3 C’sFour Questions/3 C’s Virtual MemoryVirtual Memory Toys!Toys!

2. March 2005 2R. Smith - University of St Thomas - Minnesota Processor Technology Tubes – fragile!Tubes – fragile! Transistors – big, but promisingTransistors – big, but promising ICs – thank goodness for DIPsICs – thank goodness for DIPs Sorry, no first-aid kitSorry, no first-aid kit

3. March 2005 3R. Smith - University of St Thomas - Minnesota Direct Mapped Cache The basis of today’s designsThe basis of today’s designs –A collection of high speed RAM locations –Broken into individually addressed “cache entries” –Part of RAM address chooses cache entry (“Direct mapping”) A cache entryA cache entry –“Index” is its address in the cache –Valid bit - true if the entry contains valid RAM data –“Tag” holds the address bits not matching the cache address –Data area - where the stored data resides Store multiple words (spatial locality)Store multiple words (spatial locality)

4. March 2005 4R. Smith - University of St Thomas - Minnesota Set Associative Caches That 2-way, 4-way, 8-way stuffThat 2-way, 4-way, 8-way stuff Provides multiple ‘hit’ entries per mappingProvides multiple ‘hit’ entries per mapping Problem:Problem: –Calculate size information for a set associative cache AttributesAttributes –Address size –Block size –Number of lines –N-way

5. March 2005 5R. Smith - University of St Thomas - Minnesota Fully associative cache “Association list” approach“Association list” approach –Accepts an address –Returns the data Not a RAM – stores tags and dataNot a RAM – stores tags and data –Tag field = full address – block size –Data field = data block Parallel tag field checkingParallel tag field checking –Automatically matches, retrieves data with matching tag –Expensive in terms of logic

6. March 2005 6R. Smith - University of St Thomas - Minnesota Four Questions General framework for memory hierarchiesGeneral framework for memory hierarchies 1. Where can a block be placed?1. Where can a block be placed? –Different schemes have different restrictions –Some have no restrictions (fully associative) 2. How is a block found?2. How is a block found? –Fully associative - logic does all the work in one cycle –Direct addressing does much of the work 3. How do we choose a block to replace?3. How do we choose a block to replace? –Option: Randomly –Option: LRU 4. What happens during a write?4. What happens during a write? –Write-back –Write-through

7. March 2005 7R. Smith - University of St Thomas - Minnesota Types of Misses (Three C’s) Compulsory misses or Cold start missesCompulsory misses or Cold start misses –When a block is first accessed by the program –Impossible to eliminate these –Right block size can reduce the number Capacity missesCapacity misses –Cache can’t contain all blocks needed by the program –i.e. the program keeps pulling blocks back in after they’ve been replaced by other referenced blocks –Suggests the cache isn’t big enough Conflict misses or Collision missesConflict misses or Collision misses –When multiple blocks compete for the same set/location –Happens in set associative and direct mapped –Doesn’t happen in fully associative cache

8. March 2005 8R. Smith - University of St Thomas - Minnesota “Virtual Memory” (VM) The Cache problem:The Cache problem: –Convert a RAM address into a data item The VM problem:The VM problem: –Convert a convenient RAM address into the real one Back to the old problem: Software is expensiveBack to the old problem: Software is expensive –Eliminate trouble caused by varying RAM addresses –How do we “load” a program into RAM?

9. March 2005 9R. Smith - University of St Thomas - Minnesota Memory Management Problems RelocationRelocation Storage ProtectionStorage Protection FragmentationFragmentation

10. March 2005 10R. Smith - University of St Thomas - Minnesota Assumptions User applications pose the biggest problemsUser applications pose the biggest problems Memory Management focuses on user modeMemory Management focuses on user mode –User programs run in restricted RAM –Restrictions may be turned off for the OS –I/O operations use “real” addresses

11. March 2005 11R. Smith - University of St Thomas - Minnesota #1: Base+Limit Register Memory controlled through 2 registersMemory controlled through 2 registers –Base register – sets program’s starting address –Limit register – sets program’s address space size All of the program’s addresses are relocatedAll of the program’s addresses are relocated –If greater than limit, then an error –Add base value to get ‘real’ RAM address Program can’t “see” RAM outside its areaProgram can’t “see” RAM outside its area

12. March 2005 12R. Smith - University of St Thomas - Minnesota #2: Segmentation Similar to 80x86/Pentium “segments”Similar to 80x86/Pentium “segments” –Generalization of Base+Limit A set of registers tied to high address bitsA set of registers tied to high address bits –High bits select a segment register set –Rest of address is processed like Base+Limit

13. March 2005 13R. Smith - University of St Thomas - Minnesota Fragmentation problems External fragmentationExternal fragmentation Internal fragmentationInternal fragmentation

14. March 2005 14R. Smith - University of St Thomas - Minnesota #3: Paging All “segments” are the same (small) sizeAll “segments” are the same (small) size –Minimizes the fragmentation problem –4K for example –So we don’t need a “limit” register Addresses translated with a ‘page table’Addresses translated with a ‘page table’ –High order bits select the page table entry –The selected entry points to the page in RAM –Low order bits are the offset into the page CPU must support pagingCPU must support paging –Special register points to the current page table –Gets changed when switching processes

15. March 2005 15R. Smith - University of St Thomas - Minnesota Virtual Memory Uses RAM as a cacheUses RAM as a cache –“Real” data is all on the hard drive –Pages travel to RAM from hard drive as needed –Pages sent to hard drive if not being used Page table entry (PTE) indicates optionsPage table entry (PTE) indicates options –Page is in RAM right now (“valid”) –Page is not in RAM, but on the hard drive –Page doesn’t exist Other PTE infoOther PTE info –Page has been used/read –Page is “read only” –Page is “dirty”

16. March 2005 16R. Smith - University of St Thomas - Minnesota Implications of Paging Good thingsGood things –Programs can be larger than physical RAM –Programs can’t see each others’ RAM –Bits of RAM can be shared through mapping ProblemsProblems –Thrashing and working sets –Slow translation speeds – Translation Lookaside Buffer (TLB) Yet another specialized sort of cacheYet another specialized sort of cache

17. March 2005 17R. Smith - University of St Thomas - Minnesota Page system sizing questions Size of the page table, givenSize of the page table, given –4K pages –24-bit virtual addresses –32-bit physical (“real”) RAM addresses –4 bits for valid, dirty, protected, used Size of the page table, givenSize of the page table, given –8K pages –32-bit virtual addresses –36-bit physical (“real”) RAM addresses –4 bits for valid, dirty, protected, used

18. March 2005 18R. Smith - University of St Thomas - Minnesota More toys? Magnetic storageMagnetic storage Hard DrivesHard Drives

19. March 2005 19R. Smith - University of St Thomas - Minnesota That’s it. Questions?Questions? Creative Commons License This work is licensed under the Creative Commons Attribution-Share Alike 3.0 United States License. To view a copy of this license, visit http://creativecommons.org/licenses/by-sa/3.0/us/ or send a letter to Creative Commons, 171 Second Street, Suite 300, San Francisco, California, 94105, USA.