1. Slide 1EE40 Fall 2009Prof. Cheung EE40 Final Exam Review Prof. Nathan Cheung 12/01/2009 Practice with past exams http://hkn.eecs.berkeley.edu/exam/list/?exam_course=EE%2040

2. Slide 2EE40 Fall 2009Prof. Cheung 2 Overview of Course Circuit components: R, C, L, sources I-V characteristics energy storage/dissipation Circuit analysis: Laws: Ohm’s, KVL, KCL  Equivalent circuits (series/ parallel, Thevenin, Norton)  Superposition for linear circuits  Nodal analysis  Mesh analysis  Phasor I and V First-order transient excitation/analysis: Second Order RLC circuits Bode Plots

3. Slide 3EE40 Fall 2009Prof. Cheung 3 Semiconductors Devices pn-diodes (many types) FETs (n-channel, p-channel, CMOS) Useful Diode and FET circuits: Amplifiers: op-amp (negative feedback), rectifiers; wave shaping circuits Logic gates; Combinatorial logic (sum-of-products, Karnaugh maps), sequential logic etc. Overview of Course

4. Slide 4EE40 Fall 2009Prof. Cheung Diode Circuit Analysis by Assumed Diode States 1) Specify Ideal Diode Model or Piecewise-Linear Diode Model 2) Each diode can be ON or OFF 3) Circuit containing n diodes will have 2 n states 4) The combination of states that works for ALL diodes (consistent with KVL and KCL) will be the solution reverse bias forward bias I D (A) V D (V) reverse bias forward bias I D (A) V Don

5. Slide 5EE40 Fall 2009Prof. Cheung Example Problem: Perfect Rectifier Model Sketch V out versus V in Suggested problem: What if there is a 0.6V drop when diodes are on ?

6. Slide 6EE40 Fall 2009Prof. Cheung Diode with Capacitor Circuit (e.g.Level Shifter) - V C + V OUT + - V IN + - C t 1) Diode =open, V C (t)=0, V OUT (t)= V IN (t) 2) Diode =short, V C (t)= -V IN (t), V OUT (t)=0 3) Diode =open, V C (t)= -V IN (min), V OUT (t)= V IN (t)-V IN (min) V OUT (t)= V C (t)+ V IN (t), VCVC V OUT t 1 3 2 Finds out what happens to V C when V IN changes V IN (min)

7. Slide 7EE40 Fall 2009Prof. Cheung Example: Diode with RL Circuit Answer Sketch i(t)  = L/R = 0.05 msec Note: i(t) is continuous

8. Slide 8EE40 Fall 2009Prof. Cheung Load-Line Analysis We have a circuit containing a two-terminal non-linear element “NLE”, and some linear components. 1V +-+- 250K S Non- linear element 9A9A 1M D +-+- 2V 200K S NLENLE D Then define I and V at the NLE terminals (typically associated signs) First replace the entire linear part of the circuit by its Thevenin equivalent. IDID V DS +-+-

9. Slide 9EE40 Fall 2009Prof. Cheung Example of Load-Line Analysis (con’t) And have this connected to a linear (Thévenin) circuit +-+- 2V 200K The solution ! Given the graphical properties of two terminal non-linear circuit (i.e. the graph of a two terminal device) V DS IDID  A) 10 (V) 1 2 IDID D NLENLE S Whose I-V can also be graphed on the same axes (“load line”) Application of KCL, KVL gives circuit solution +-+- 2V 200K S NLENLE D IDID V DS +-+-

10. Slide 10EE40 Fall 2009Prof. Cheung Example : Voltage controlled Attenuator V C and R C Determines r d at Q point of diode

11. Slide 11EE40 Fall 2009Prof. Cheung The large capacitors and DC bias source are effective shorts for the ac signal in small-signal circuits Example : Voltage Controlled Attenuator

12. Slide 12EE40 Fall 2009Prof. Cheung 12 V DS IDID  A) 10 (V) 1 2 Three-Terminal Parametric Graphs Concept of 3-Terminal Parametric Graphs: We set a voltage (or current) at one set of terminals (here we will apply a fixed V GS, IG=0) and conceptually draw a box around the device with only two terminals emerging so we can again plot the two-terminal characteristic (here I D versus V DS ). 3-Terminal Device IDID D G S V GS +-+- V GS = 3 V GS = 2 V GS = 1 But we can do this for a variety of values of V GS with the result that we get a family of curves.

13. Slide 13EE40 Fall 2009Prof. Cheung 13 Graphical Solutions for 3-Terminal Devices Now draw I D vs V DS for the 2V - 200K  Thevenin source. First select V GS (e.g. 2V) and draw I D vs V DS for the 3-Terminal device. V DS IDID  A) 10 (V) 1 2 V GS = 3 V GS = 2 V GS = 1 IDID G +-+- +-+- V 2V D 200K S V DS IDID  A) 10 (V) 1 2 The only point on the I vs V plane which obeys KCL and KVL is I D = 5  A at V DS = 1V. The solution ! We can only find a solution for one input (V GS ) at a time:

14. Slide 14EE40 Fall 2009Prof. Cheung 1)Guess the mode of operation for the transistor. (We will learn how to make educated guesses). 2)Write the I D vs. V DS equation for this guess mode of operation. 3)Use KVL, KCL, etc. to come up with an equation relating I D and V DS based on the surrounding linear circuit. 4)Solve these equations for I D and V DS. 5)Check to see if the values for I D and V DS are possible for the mode you guessed for the transistor. If the values are possible for the mode guessed, stop, problem solved. If the values are impossible, go back to Step 1. SOLVING MOSFET CIRCUITS: STEPS

15. Slide 15EE40 Fall 2009Prof. Cheung CHECKING THE ANSWERS NMOS 1) V GS > V T(N) in triode or saturation V GS ≤ V T(N) in cutoff 2) V DS < V GS – V T(N) in triode V DS ≥ V GS – V T(N) in saturation Triode Saturation Cut-off PMOS 1) V GS < V T(P) in triode or saturation V GS ≥ V T(P) in cutoff 2) V DS > V GS – V T(P) in triode V DS ≤ V GS – V T(P) in saturation Triode Saturation Cut-off

16. Slide 16EE40 Fall 2009Prof. Cheung Example Problem : MOSFET Circuit

17. Slide 17EE40 Fall 2009Prof. Cheung Find V GS such that V DS =2V Example Problem : MOSFET Circuit Answer Check: V DS (=2V) > V GS -V T (=1.5-0.5=1V) MOSFET indeed is in saturation mode Guess Saturation Mode

18. Slide 18EE40 Fall 2009Prof. Cheung Find small-signal model parameters Example Problem : MOSFET Circuit =10 -5 Siemens

19. Slide 19EE40 Fall 2009Prof. Cheung How do you guess the right mode ? Often, the key is the value of V GS. (We can often find V GS directly without solving the whole circuit.) V GS ≤ V T(N) definitely cutoff V DS IDID V GS = V T(N) +  probably saturation V DS IDID V GS - V T(N) = 

20. Slide 20EE40 Fall 2009Prof. Cheung triode mode saturation mode V DS V GS - V TH(N) When V GS >> V TH(N), it’s harder to guess the mode. IDID If I D is small, probably triode mode How do you guess the right mode ?

21. Slide 21EE40 Fall 2009Prof. Cheung EXAMPLE G D S IDID + V GS _ + V DS _ +_+_ +_+_ 4 V 3 V 1.5 k  GIVEN: V TH(N) = 1 V, K= 250  A/V 2, = 0 V -1. 1) Since V GS > V TH(N), not in cutoff mode. Guess saturation mode. 2) Write transistor I D vs. V DS : 3)Write I D vs. V DS equation using KVL:

22. Slide 22EE40 Fall 2009Prof. Cheung EXAMPLE G D S IDID + V GS _ + V DS _ +_+_ +_+_ 4 V 3 V 1.5 k  GIVEN: V TH(N) = 1 V, ½ W/L  n C OX = 250  A/V 2, = 0 V -1. 4) Solve V DS : I D = 1mA V DS = 2.5 V 5) Check: I D and V DS are correct sign, and V DS ≥ V GS -V T(N) as required in saturation mode.

23. Slide 23EE40 Fall 2009Prof. Cheung G D S IDID + V GS _ + V DS _ +_+_ +_+_ 4 V 3 V 1.5 k  GIVEN: V TH(N) = 1 V, K= 250  A/V 2, = 0 V -1. WHAT IF WE GUESSED THE MODE WRONG? 1) Since V GS > V TH(N), not in cutoff mode. Guess triode mode. 2) Write transistor I D vs. V DS : 3)Write I D vs. V DS equation using KVL: I D = 2·250·10 -6 (3 – 1 – V DS /2)V DS

24. Slide 24EE40 Fall 2009Prof. Cheung G D S IDID + V GS _ + V DS _ +_+_ +_+_ 4 V 3 V 1.5 k  GIVEN: V TH(N) = 1 V, K= 250  A/V 2, = 0 V -1. 4) Solve for V DS with quadratic equation by combining 2) and 3): V DS = {4 V, 2.67 V} 5) Check: V DS > V GS – V T(N) = 2V Neither value valid in triode mode! Guess is incorrect. WHAT IF WE GUESSED THE MODE WRONG?

25. Slide 25EE40 Fall 2009Prof. Cheung G D S IDID + V GS _ + V DS _ +_+_ +_+_ 4 V 3 V 1.5 k  In this circuit, the transistor delivered a constant current I DSAT to the 1.5 k  resistor. This circuit acts like a constant current source, as long as the transistor remains in saturation mode. I DSAT does not depend on the attached resistance if saturation is maintained. I DSAT 1.5 k  Another Perspective

26. Slide 26EE40 Fall 2009Prof. Cheung G D S IDID + V GS _ + V DS _ +_+_ +_+_ V DD V GS RLRL I DSAT does depend on V GS ; one can adjust the current supplied by adjusting V GS. The circuit will go out of saturation mode if V GS < V T(N) or V DS < V GS – V T(N) This can happen if V GS is too large or too small, or if the load resistance is too large. I DSAT RLRL Another Perspective

27. Slide 27EE40 Fall 2009Prof. Cheung ANOTHER EXAMPLE G D S IDID + V GS _ + V DS _ +_+_ 4 V 1.5 k  GIVEN: V TH(N) = 1 V, K= 250  A/V 2, = 0 V -1. 1) What is V GS ? No current goes into/out gate. V GS = 3 V by voltage division. Guess saturation (randomly). 2) Write transistor I D vs. V DS : 3)Write I D vs. V DS equation using KVL: 2 k  6 k  Effectively the same circuit as previous example: only 1 voltage source in this case V DS =2.75V consisitent with saturation mode

28. Slide 28EE40 Fall 2009Prof. Cheung The CMOS Inverter: Current Flow V IN V OUT V DD 0 0 N: off P: Triode N: Triode P: off N: Triode P: sat N: sat P: Triode N: sat P: sat A BDE Ci I S D G G S D V DD V OUT V IN

29. Slide 29EE40 Fall 2009Prof. Cheung Another CMOS Example: The LATCH V DD V OUT V DD V OUT_INT CLK V IN Data (V IN ) is written to the internal node (V OUT_INT ) when the clock is low. V OUT remains frozen. When the clock is high. The (inverted) internal node voltage is written to V OUT. The internal node V OUT_INT remains frozen

30. Slide 30EE40 Fall 2009Prof. Cheung THE LATCH V DD V OUT V DD V OUT_INT CLK V IN When CLK is low the left- hand transistors conduct. The right-hand transistors are open. V OUT_INT is charged to V IN. 0 V V DD 0 V V DD V OUT remains the same; there is no charging path.

31. Slide 31EE40 Fall 2009Prof. Cheung THE LATCH V DD V OUT V DD V OUT_INT CLK V IN When CLK is high, the right-hand transistors conduct. the left-hand transistors are open. V DD 0 V V OUT_INT remains the same; there is no charging path. V OUT is changed to V OUT_INT.

32. Slide 32EE40 Fall 2009Prof. Cheung CONCEPT OF STATE V DD Current State V DD Next State CLK V IN A latch stores a “1” or “0”. The stored value is known as the “state”. This is one of the basic elements needed to make a “state machine” (covered in EE 20 and CS 61C).

33. Slide 33EE40 Fall 2009Prof. Cheung LATCH AS GATEKEEPER Combinatorial Logic Signal propagates all the way through Includes our logic gates: NAND, NOT, etc. Sequential Element Prevents changes in output until signaled A signal may have to go through a complex system of gates, with paths of different delays: possibility of false output!

34. Slide 34EE40 Fall 2009Prof. Cheung Amplifier Efficiency Power Supply A Power Supply B Load Source P i = (10 -3 V) 2 /10 5  =10 -11 W Load P 0 = (8V) 2 /8  =8 W Power Supplies P s = 15W+7.5W = 22.5 W Amplifier P d = 22.5W+10 -11 W-8W = 14.5 W Amplifier Amplifier Efficiency  = 8/22.5 =36%

35. Slide 35EE40 Fall 2009Prof. Cheung Differential Signal and Common Mode Signal Redefine the inputs in terms of two other voltages: 1. differential mode input v id  v i1 – v i2 2. common mode input v icm  (v i1 + v i2 )/2 so that v i1 = v icm + (v id /2) and v i2 = v icm - (v id /2) “common mode gain” “differential mode gain”

36. Slide 36EE40 Fall 2009Prof. Cheung Common Mode Rejection Ratio Example Differential signal from sensor = 1mV (peak). We want outputs signal > 1V implies A d > 1000 Common mode signal =100V (from power line). We want common mode signal < 0.1V implies A cm <10 -4 Therefore CMRR needs to be > 20log(10 7 )= 140dB

37. Slide 37EE40 Fall 2009Prof. Cheung Given V off =2mV I B = 100nA I off = 20nA A cm =1 A d =100 Both input terminals to ground through 100k  resistors Use superposition Vo = A d (V voff +V Ioff )+ A cm v icm = 100(0.001667+0.001667)+1(0.01)=0.3343V Offset Voltage, Offset Current, and Bias Current