1. 4-bit adder, multiplexer, timing diagrams, propagation delays
CSE 140L Lecture 3
4-bit adder, multiplexer, timing diagrams, propagation delays
CK Cheng

2. Timing behavior Real circuits have delays
Gate delay – time for an output of the gate to change after its input changes
We can simulate timing delays in Quartus II to see these delays

3. Gate delay Notice rise time, fall time, and gate delay: input output

4. Quartus II Timing Simulation
Notice the glitches and delay in the output

5. 4-bit Ripple Carry Adders
Chain 4 1-bit full adders together. Connect the carry-out of the previous adder and the carry-in of the next adder.
Worst delay path (critical path): from A0, B0, or C0 to S3, or C4

6. Critical Path for worst delay
Propagation from C0 to C4
C4 changes as C0 toggles C0
1110
0001 C4

7. Multiplexers
-Multiplexers (MUXes) are like selectors. There is one output, 2 or more inputs, and a “selector” input that determines which of those inputs gets outputed.
-Allows several devices to share one single line.
This is a 2:1 mux. It has 2 inputs, 1 output. Because there are only 2 inputs, S is one bit. If S=0, then we output A. If S=1, then we output B. A
MUX Z B S

8. Multiplexers -The truth table for the 1-bit 2:1 MUX.
When S=0, the MUX will select A as its output. It doesn’t matter what B is. Likewise, When S=1, B is selected as output. S A B Z 1
The boolean equation:
Z = AS’ + BS

9. Multiplexers
-If S is 0, then I0 will pass and I1 is blocked. Thus, y=I0.
-Likewise, if S is 1, y=I1.

10. Multiplexers -We can also make a 4:1 MUX using three 2:1 MUX
If S1S0 = 00, then S1 will select MUX from A and B. Since S0=0, Z= A. A
MUX B 1
MUX Z S0 Z 1 C
MUX S1 D 1

11. Multiplexers -We can make 4:1 and above MUXes too.
-With 4 inputs, our selector needs to have two bits.

12. Exercises Subtractors: a. Subtraction b. One’s Complement
c. Two’s Complement