1. Encryption Transaction with 3DES Team W2 Yervant Dermenjian (W21) Taewan Kim (W22) Evan Mengstab(W23) Xiaochun Zhu(W24) Objective: To implement a secure credit card transaction using 3DES encryption using Kerberos-style authentication. Current Stage: Basic Component Layout 02/18/2004 Current Stage: Basic Component Layout 02/18/2004 Design Manager: Rebecca Miller

2. Current Status  Design Proposal (100% done)  Architecture Proposal (100% done)  Size Estimate and Floor Plan (100% done)  Full-chip Transistor-level Schematic (100% done)  Component Layout Another new Floor Plan Another new Floor Plan Basic components (100% done) Basic components (100% done)  To be done Spice Simulation Spice Simulation Layout of larger blocks (90% done) Layout of larger blocks (90% done) Some permutations layouts Some permutations layouts Top-Level layout routing Top-Level layout routing

3. Revised Architecture KeyReg 56’b Register 32’b 32’b input Enc_ShiftL Dec_ShiftR IP -1 wiring PC-2 Wiring 56->48 IP wiring Text 64’b Register Expand 32->48 wiring S-Box 512 x 4’b P 32->32 wiring PC (wiring) 32’b Latch 2:1 mux Sub_rnd e/d txt_in ready key_in Sh_d Sh_e 32 64 32 “R” “L” R L 56 48 32 wr_en OUT ready 32 2:1 mux 32 64 2:1mux 32’b Latch

4. Top Level “des3”

5. Updated Floorplan 32’b Latch PC1 Mux 56’b Key Reg PC2 IP Mux IP-1 32’b Text Register (L) 32’b Text Register (R) 32’b Mux 32’b XOR Expand 48’b XOR P SBOX Right Shift Left Shift Right Shift Left Shift 32’b Mux All large functional blocks use Metal 1 and Metal 2. M1 M2 M3 M4 Input Mux Output Program Control clock 416μm 360μm

6. Pin Connections / Porosity

8. Project Goals Implement fully functioning 3DES Chip Implement fully functioning 3DES Chip Speeds high enough for credit card transactions Speeds high enough for credit card transactions Dense design for small area Dense design for small area

9. Inverter / Buffer

10. Exclusive OR

11. D Latch

12. 2:1 Multiplexor

13. D Flip Flops Enable / Reset asserted high No Enable / Reset asserted high

14. Half Adder

15. Left Barrel Shifter

16. Right Barrel Shifter

17. Program Control

18. 56’b Key Register

19. 32’b Latch

20. 32’b Exclusive OR

21. 32’b 2:1 Multiplexor

22. PC1 Permutation

23. 64’b Text Register

24. SBOX1 ROM

25. Updated Transistor Counts and Area

27. Area0.2028 mm 2 Transistors15,238 Density0.08 trans/μm 2

28. Design Decisions  Stick with hardwiring for permutations  Inputs and outputs on same side  Layed out in one long row of skinny modules

29. Questions ?