1. [M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Mon. Nov. 24 Overall Project Objective : Dynamic Control The Traffic Lights

2. Status  Design Proposal  Chip Architecture  Behavioral Verilog Implementation  Size estimates  Floorplanning  Behavioral Verilog simulated  Gate Level Design  Component Layout/Simulation  Chip Layout  Complete Simulation

3. Data Input Initial Values Clock Operation T, Left-Turn Counter R, r, R_ L, r_ l Flow Control FSM Light Contro l FSM Selection

4. Old Schematic Simulation

5. Current Schematic Simulation

6. Tom’s FSM  Simulation results (missed them last time)  A few glitches in next state logic  Doesn’t affect the operation  Flops smooth them out  Everything works well  Adding some buffers for high fan-out outputs  We left out a flipflop in the top level schematic, so I’m putting it in my fsm  Passes DRC, LVS, and extracted RC analog simulation

7. Tom’s FSM

10. Simulation Problems  Since we use a “real time” clock, the schematic has to run for a long time  Every test takes hours  Minor errors in wiring and a miscommunication about the comparator messed up simulations

11. Issues  Still working on getting simulations to work on Cadence ’ s spectre  Spectre is really slow, (several hours to run one simulation test)  We never hooked up all the schematics together and ran spectre simulations on it  We know it works logically in Verilog when we divided up the work  Some Global interconnects need to be finished.

12. Old Version

14. NEW

15. Global Routing + LVS  Before, I finished all single blocks LVS.  For checking millions of wires global routing, and we got a over 300+ wire need to route. So I try to combine single blocks, make it bigger and bigger, then try to pass LVS.  After finish schematic simulation, we also add some logic beside our big blocks. Need to add them in our whole floorplan

16. Counters Shift Registers MUX

17. Control Registers

18. Counters : Calculate how many cars leaving

19. Update our schematic : We need to compare A “greater” than B. So there are some changing in block.

20. New Layout 8 bits Comparator A little bigger than before.

21. New Layout Some other Single blocks. (Real time counter, MUX, comparator…etc) Just combine them together and pass LVS.

22. NEW

23. Global Routing  Thank God. The global routing for 2:1 MUX to 16:1 MUX are finished! DRC and LVS clean.  Keep working on connecting adjacent blocks as soon as possible.

24. Global Routing Connected blocks in the view of schematic. About Half of the chip.

25. Global Routing The space for routing is pretty close to the estimation in floor plan. Some additional wires are used for global signals, such as clock, set, and reset.

26. Result  ALU, two FSM have not been connected. It shouldn’t take too much time.  Hopefully we can make it on time!

27. Question ?