1. Team W1 Design Manager: Rebecca Miller 1. Bobby Colyer (W11) 2. Jeffrey Kuo (W12) 3. Myron Kwai (W13) 4. Shirlene Lim (W14) Stage IV: February 18 h 2004 COMPONENT LAYOUT Presentation #5: Rijndael Encryption Overall Project Objective: Implement the new AES Rijndael algorithm on chip 18-525 Integrated Circuit Design Project

2. Status  Design Proposal  Architecture Proposal  Size Estimates/Floorplan  Gate Level Design  Schematic Design (Fixed)  Input/Output Logic to SBOX Changed and Tested  Top Level Schematic Verified  Component Layout (90% Done)  To be Done  Simulations/Optimizations  Everything else… 18-525 Integrated Circuit Design Project

3. Design Decisions & Problems DECISIONS Change Verilog to match newer input control logic to SBOX Control Logic will be made of PMOS, can’t be done in Verilog Implemented clock divider using counters Added 3 rd SBOX Removed 5 Rounds of Encryption PROBLEMS New SBOX logic and reduced pipeline implementation into Verilog Accidentally left SBOX lookup in FinalTextOut, looked into ROM twice Logic In into the SBOX Tree Structure – Not so nice in layout Schematic Simulation yields correct output, but timing issues are causing problems in the pipeline 18-525 Integrated Circuit Design Project

4. OLD FLOORPLAN 18-525 Integrated Circuit Design Project

6. ADDED SBOX #3 -Previous design inefficient for small text -Makes Sense to Give Round Key Generation its own SBOX - But increased transistor count drastically to ~45k -The logic and muxes are HUGE 18-525 Integrated Circuit Design Project

7. ELIMINATION - Eliminate 5 rounds - Eliminate 1 SBOX & control logic - Reduce transistor count to 27k 18-525 Integrated Circuit Design Project

8. New Schematic (5 Rounds) Mux used in both In and Out logic, moved outside and shared

9. module logicandsbox (Out, In); output [7:0] Out; input [7:0] In; reg[7:0]Out; always @(In) case(In)// synopsys full_case parallel_case 8'h00: Out=8'h63; 8'h01: Out=8'h7c; 8'h02: Out=8'h77; 8'h03: Out=8'h7b; 8'h04: Out=8'hf2; 8'h05: Out=8'h6b; 8'h06: Out=8'h6f; 8'h07: Out=8'hc5; 8'h08: Out=8'h30; 8'h09: Out=8'h01; 8'h0a: Out=8'h67; 8'h0b: Out=8'h2b; 8'h0c: Out=8'hfe; 8'h0d: Out=8'hd7; 8'h0e: Out=8'hab; FUNCTIONAL MODEL OF ROM Case Statements 18-525 Integrated Circuit Design Project

10. Floorplan 18-525 Integrated Circuit Design Project ROM and Control Key Expand no pipe In Logic & Out Logic Round Permutations Key Expand Text & Key Output 345 um x 325 um

11. ROM Schematic 18-525 Integrated Circuit Design Project

12. ROM Control with PMOS 18-525 Integrated Circuit Design Project

13. ROM and Control Logic 18-525 Integrated Circuit Design Project ROM Control Logic

14. Round Permutation 18-525 Integrated Circuit Design Project

15. Key Expand 18-525 Integrated Circuit Design Project

16. Key Expand Layout 18-525 Integrated Circuit Design Project

17. SBox Mux Tree In-Logic 18-525 Integrated Circuit Design Project 8 x Mux5 Previous Logic

18. SBox Mux Tree In-Logic 18-525 Integrated Circuit Design Project Current Logic

19. SBox Mux Tree In-Logic 18-525 Integrated Circuit Design Project Current Logic Tree Structure Difficult to Implement in Layout Need to finalize wiring from other modules in order to be more efficient in arranging in-logic

20. SBox Mux Tree Out-Logic 18-525 Integrated Circuit Design Project

21. Schematic Simulation Results e0 34 e7 8b 18-525 Integrated Circuit Design Project

22. Schematic Simulation Results 18-525 Integrated Circuit Design Project

23. COMPONENTS AREA ESTIMATE ( um 2 ) Key Schedule  Registers & XORs 351 um x 70 um = 24,570 um 2 ROM  SBOX (2) 50 um x 170 um x 2 = 14,000 um 2  Control Logic (352 um x 70 um) – 14,000 um 2 = 10,640 um 2 Transformation  Register & XORs 160 um x 352 um = 56,320 um 2 Others  Buffers & Wiring 10% = 10,553 um 2 TOTAL 116,083 um 2 (~350 um x ~350 um) PREVIOUS AREA ESTIMATE

24. 18-525 Integrated Circuit Design Project COMPONENTS AREA ESTIMATE ( um 2 ) Key Schedule  Registers & XORs 80 um x 40 um x 4 um + 35 um x40 um = 14,200 um 2 ROM  SBOX and Control Logic (2) 60 um x 250 um x 2 = 30,000 um 2 Transformation  Register & XORs 70 um x 70 x 4 = 19,600 um 2 Add Round Key & Final Text Out 70 um x 15 um x 2 = 2100 um 2 Others  Buffers & Wiring 10% = 6,590 um 2 CURRENT AREA DIMENSIONS Total: 345 um x 325 um (taken from current floorplan)

25. Previous PROBLEMATIC Transistor Count (Assuming 32-bit Implementation)  Clock Divider 165  Add Round Key 256  Valid Out DFFs (10) 266  SBoxMuxTreeIn (3) 7008  SBoxMuxTreeOut(3) 11976  ROM (3) 7644  Key Expansion (10) 3840  Round Permutation (9) 11952  Final Text Out 256 Total: 47523 Total with Buffer Estimate (10%) 52275 Changing the ROM Control to PMOS 47211 18-525 Integrated Circuit Design Project

26. Current Transistor Count with 5 Rounds of Encryption (Assuming 32-bit Implementation)  Clock Divider 165  Add Round Key 256  Valid Out DFFs (5) 136  SBoxMuxTreeIn (Text) 2336  SBoxMuxTreeIn (Key) 1056  SBoxMuxTreeOut (Text) 3992  SBoxMuxTreeOut (Key) 2038  ROM with New Control Logic (3) 7332  Key Expansion (5) 1920  Round Permutation (4) 5312  Final Text Out 256 Total: 24799 Total with Buffer Estimate (10%) 27278 18-525 Integrated Circuit Design Project

27. Alternative Implementations Transistor Count (Assuming 32-bit Implementation)  Current ~52,275  Minus 1 SBOX & Logic ~37,985  Minus 5 rounds & 1 SBOX and logic ~27,278 18-525 Integrated Circuit Design Project

28. Questions? Answers??? 18-525 Integrated Circuit Design Project