Presentation is loading. Please wait.

Presentation is loading. Please wait.

CSCE 212 Quiz 11 – 4/13/11 Given a direct-mapped cache with 8 one-word blocks and the following 32-bit memory address references: 1 2, 10000110 2, 11010100.

Published by Modified over 9 years ago

Similar presentations

Presentation on theme: "CSCE 212 Quiz 11 – 4/13/11 Given a direct-mapped cache with 8 one-word blocks and the following 32-bit memory address references: 1 2, 10000110 2, 11010100."— Presentation transcript:

1 CSCE 212 Quiz 11 – 4/13/11 Given a direct-mapped cache with 8 one-word blocks and the following 32-bit memory address references: 1 2, 10000110 2, 11010100 2, 1 2, 10000111 2 Show the final state of the cache after the accesses and tell whether each reference is a hit or miss. *You will need to show the block index, valid bit, tag, and data. Don’t worry about leading zeros in the tag. EC: Do the same for a cache with 4 two-word blocks.

2 CSCE 212 Quiz 11 Answers 1 2, 10000110 2, 11010100 2, 1 2, 10000111 2 M MM H M IndexVTagData 0N 1Y... 00000Memory(1) 2N 3N 4Y... 11010Memory(11010100) 5N 6Y... 10000Memory(10000110) 7Y... 10000Memory(10000111)

3 CSCE 212 Quiz 11 Answers 1 2, 10000110 2, 11010100 2, 1 2, 10000111 2 M MM H H IndexVTagData 0Y... 00000Memory(0) Y... 00000Memory(1) 1N N 2Y... 11010Memory(11010100) Y... 11010Memory(11010101) 3Y... 10000Memory(10000110) Y... 10000Memory(10000111)

Download ppt "CSCE 212 Quiz 11 – 4/13/11 Given a direct-mapped cache with 8 one-word blocks and the following 32-bit memory address references: 1 2, 10000110 2, 11010100."

Similar presentations

Cache Memory Exercises. Questions I Given: –memory is little-endian and byte addressable; memory size; –number of cache blocks, size of cache block –An.

Cache Memory Exercises. Questions I Given: –memory is little-endian and byte addressable; memory size; –number of cache blocks, size of cache block –An.
Malloc & VM By sseshadr. Agenda Administration – Process lab code will be inked by Thursday (pick up in ECE hub) – Malloc due soon (Thursday, November.

Malloc & VM By sseshadr. Agenda Administration – Process lab code will be inked by Thursday (pick up in ECE hub) – Malloc due soon (Thursday, November.
Recitation 7 Caching By yzhuang. Announcements Pick up your exam from ECE course hub ◦ Average is 43/60 ◦ Final Grade computation? See syllabus

Recitation 7 Caching By yzhuang. Announcements Pick up your exam from ECE course hub ◦ Average is 43/60 ◦ Final Grade computation? See syllabus
CSC1016 Coursework Clarification Derek Mortimer March 2010.

CSC1016 Coursework Clarification Derek Mortimer March 2010.
Using one level of Cache:

Using one level of Cache:
The Lord of the Cache Project 3. Caches Three common cache designs: Direct-Mapped store in exactly one cache line Fully Associative store in any cache.

The Lord of the Cache Project 3. Caches Three common cache designs: Direct-Mapped store in exactly one cache line Fully Associative store in any cache.
15-447 Computer ArchitectureFall 2007 © November 14th, 2007 Majd F. Sakr CS-447– Computer Architecture.

Computer ArchitectureFall 2007 © November 14th, 2007 Majd F. Sakr CS-447– Computer Architecture.
CS61C L31 Caches II (1) Garcia, Fall 2006 © UCB GPUs >> CPUs?  Many are using graphics processing units on graphics cards for high-performance computing.

CS61C L31 Caches II (1) Garcia, Fall 2006 © UCB GPUs >> CPUs?  Many are using graphics processing units on graphics cards for high-performance computing.
How caches take advantage of Temporal locality

How caches take advantage of Temporal locality
Memory Hierarchies Exercises [7.1-7.3] Describe the general characteristics of a program that would exhibit very little spatial or temporal locality with.

Memory Hierarchies Exercises [ ] Describe the general characteristics of a program that would exhibit very little spatial or temporal locality with.
CSCE 212 Quiz 8 – 3/23/11 1.What type of element is the ALU (combinational or state) and what does it mean for an element to be that type? 2.What is the.

CSCE 212 Quiz 8 – 3/23/11 1.What type of element is the ALU (combinational or state) and what does it mean for an element to be that type? 2.What is the.
COMP3221: Microprocessors and Embedded Systems Lecture 26: Cache - II Lecturer: Hui Wu Session 2, 2005 Modified from.

COMP3221: Microprocessors and Embedded Systems Lecture 26: Cache - II Lecturer: Hui Wu Session 2, 2005 Modified from.
LRU Replacement Policy Counters Method Example

LRU Replacement Policy Counters Method Example
15-447 Computer ArchitectureFall 2007 © November 12th, 2007 Majd F. Sakr CS-447– Computer Architecture.

Computer ArchitectureFall 2007 © November 12th, 2007 Majd F. Sakr CS-447– Computer Architecture.
Caches The principle that states that if data is used, its neighbor will likely be used soon.

Caches The principle that states that if data is used, its neighbor will likely be used soon.
CS 61C L21 Caches II (1) Garcia, Spring 2004 © UCB Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia inst.eecs.berkeley.edu/~cs61c CS61C : Machine.

CS 61C L21 Caches II (1) Garcia, Spring 2004 © UCB Lecturer PSOE Dan Garcia inst.eecs.berkeley.edu/~cs61c CS61C : Machine.
Direct Map Cache Tracing Exercise. Exercise #1: Setup Information CS2100 Cache I 2 Memory 4GB Memory Address 310N-1N Block Number Offset 1 Block = 8 bytes.

Direct Map Cache Tracing Exercise. Exercise #1: Setup Information CS2100 Cache I 2 Memory 4GB Memory Address 310N-1N Block Number Offset 1 Block = 8 bytes.
5/27/99 Ashish Sabharwal1 Cache Misses - The 3 C’s n Compulsory misses –cold start –don’t have a choice –except that by increasing block size, can reduce.

5/27/99 Ashish Sabharwal1 Cache Misses - The 3 C’s n Compulsory misses –cold start –don’t have a choice –except that by increasing block size, can reduce.
COEN 180 Main Memory Cache Architectures. Basics Speed difference between cache and memory is small. Therefore:  Cache algorithms need to be implemented.

COEN 180 Main Memory Cache Architectures. Basics Speed difference between cache and memory is small. Therefore:  Cache algorithms need to be implemented.
Lecture 31: Chapter 5 Today’s topic –Direct mapped cache Reminder –HW8 due 11/21/2014 1.

Lecture 31: Chapter 5 Today’s topic –Direct mapped cache Reminder –HW8 due 11/21/

Similar presentations

Ads by Google