1. GPS Waypoint Navigation Team M-2: Charles Norman (M2-1) Julio Segundo (M2-2) Nan Li (M2-3) Shanshan Ma (M2-4) Design Manager: Zack Menegakis Presentation 3: Size Estimates/Floorplan February 6, 2006 Overall Project Objective: Design a chip that navigates an aircraft to pre-determined waypoints.

2. Status Design Proposal Design Proposal Project chosen Project chosen Architecture Proposal Architecture Proposal MATLAB simulated MATLAB simulated Behavioral Verilog written Behavioral Verilog written Behavioral Verilog simulated Behavioral Verilog simulated Floorplan Floorplan Structural Verilog written Structural Verilog written  Structural Verilog simulated Floorplan and more accurate transistor count Floorplan and more accurate transistor count  Schematic Design  Layout  Simulations

3. Design Decisions  Accuracy –Speed ~ 1 knot –Angle ~1 degree –Altitude ~1 feet –GPS ~1 second (105 feet) –No Look-Up Tables –Black Box Calculator for Square Root and atan2 –Effects Verification  Power –On/Off Power Control for Logic Modules

4. Design Decisions  Inputs –Latitude & Longitude Coordinates : 46 bits total  Latitude : -180˚ to 180˚, Longitude : -90˚ to 90˚  Degrees : 9-bit 2's complement  Minutes : 7-bit 2's complement  Seconds : 7-bit 2's complement –Speed :10-bit unsigned (knots) –Altitude : 15-bit unsigned (feet) –Mode : 2-bit unsigned  Outputs –Angle Correction : 9-bit 2’s complement –Speed Correction : 11-bit 2’s complement –Altitude Correction : 16-bit 2’s complement  Total –109 bits

5. Block Level System Diagram Pre-Black Box Post Black Box

6. Floorplan

7. Transistor Estimates Component Number of Transistors Recent Count FSM100214 SRAM35502220 Registers25001812 Speed Comparator Angle Comparator Altitude Comparator Waypoint Comparator 23753603966302500 Heading Calculator 12801304 Distance Calculator 26502012 Speed Calculator 950778 (2)Sexagesimal/Decimal Converter 30002658 Total16,70517,542

8. Area Estimates Component Area (µm 2 ) FSM1,700 SRAM7,000 Registers2,450 Speed Comparator Angle Comparator Altitude Comparator Waypoint Comparator 1,9001,7003,30015,000 Heading Calculator 7,000 Distance Calculator 8,500 Speed Calculator 4,100 (2) Sexagesimal/Decimal Converter 13,000 Total78,650

9. Structural Verilog module heading ( output [6:0] lat_change, lon_change, input [5:0] prelon_min, prelon_sec, prelat_min, prelat_sec, input [5:0] curlat_min, curlat_sec, curlon_min, curlon_sec, input control); wire [6:0] lat_sec,lon_sec,lat_min,lon_min,lat,lon,afinal,ofinal; sub6 as(lat_sec, curlat_sec, prelat_sec); sub6 os(lon_sec, curlon_sec, prelon_sec); sub6 am(lat_min, curlat_min, prelat_min); sub6 om(lon_min, curlon_min, prelon_min); //taking care of the +/-60 degree cases //only need to consider the 6,4,3,2 bit not (lat[6],lat_sec[6]); not (lat[2],lat_sec[2]); xor (ax62,lat_sec[6],lat_sec[2]); //can switch both to nxor xor (lat[3],ax62,lat_sec[3]); //if wanted xor (ax63,lat_sec[6],lat_sec[3]); and (ax,ax62,ax63); xor (lat[4],lat_sec[4],ax); //affect 4 cases but only 2 apply buf (lat[0],lat_sec[0]); buf (lat[1],lat_sec[1]); buf (lat[5],lat_sec[5]); ……… and_super actrl(lat_change, afinal, control); and_super octrl(lon_change, ofinal, control); endmodule module sub6 (Out, A, B); //6*34+7*2=218 transistors, 1267.76 output [6:0] Out; //2's complement input [5:0] A, B; //unsigned not (n0, B[0]); not (n1, B[1]); not (n2, B[2]); not (n3, B[3]); not (n4, B[4]); not (n5, B[5]); fa f1(Out[0], c0, A[0], n0, 1'b1); fa f2(Out[1], c1, A[1], n1, c0); fa f3(Out[2], c2, A[2], n2, c1); fa f4(Out[3], c3, A[3], n3, c2); fa f5(Out[4], c4, A[4], n4, c3); fa f6(Out[5], c5, A[5], n5, c4); not (Out[6], c5); /* always@* begin $monitor ( "%d %d", $time, Out); end */ endmodule //sub6111

10. Metal Directions Vdd, Gnd, Local Interconnect Metal 1: Horizontal Metal 2: Vertical Clk, Global Interconnect Metal 3: Horizontal Metal 4: Vertical

11. Problems  Clock Speed –1Hz too slow? –Lowest Supported Speed 65 knots –Typical UAV Cruising Speed is 70-100 knots  Pins v. Accuracy –109 Pins –Series not an option, room for error from GPS

12. What’s Next… Here’s what’s on our agenda for next week…  Reduce Pins?  Simulate Structural Verilog  Optimize Logic  Produce Module Schematics

13. Questions? Comments? Ideas?