1. Digital Logic Review
Discussion D8.7

2. Positional Notation N = P4P3P2P1P0 = P4b4 + P3b3 + P2b2 + P1b1 + P0b0
Binary
= 1 x x x x x 20 =
= 2210

3. Positional Notation N = P4P3P2P1P0 = P4b4 + P3b3 + P2b2 + P1b1 + P0b0
Hex
3AF16 = 3 x A x F x 160
= 3 x x x 1 =
= 94310

4. Binary Hex
6 A 8
F C

5. Finding 2’s Complement Complement remaining bits Copy all bits
to first 1 1 1 1
2’s complement

6. Negative Number Take 2’s ComplementFF
-4B B4 +1 B5

8. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate
XNOR Gate

9. Basic Gates Y = ~X not(Y,X) NOT Z = X & Y and(Z,X,Y) AND Z = X | Y OR1
Y = ~X
not(Y,X) X Y
NOT
X Y Z X
Z = X & Y
and(Z,X,Y)
AND Z Y
X Y Z X
Z = X | Y
or(Z,X,Y) OR Z Y
Any logic circuit can be created using only these three gates

10. NOT Gate X ~X ~~X 0 1 0 1 0 1 X ~X ~~X = X Behavior:
Behavior:
The output of a NOT gate is the inverse (one’s complement) of the input

11. AND Gate
Behavior:
The output of an AND gate is HIGH only if all inputs are HIGH
assign Z = X[1] & X[2] & ... & X[n];
assign Z = &X;
and(Z,X[1],X[2],...,X[n]);

12. OR Gate
Behavior:
The output of an OR gate is LOW only if all inputs are LOW
assign Z = X[1] | X[2] | ... | X[n];
assign Z = |X;
or(Z,X[1],X[2],...,X[n]);

13. Exclusive-OR (XOR) Gate
Behavior:
The output of an XOR gate is HIGH
only if the number of HIGH inputs is ODD
assign Z = X[1] ^ X[2] ^ ... ^ X[n];
assign Z = ^X;
xor(Z,X[1],X[2],...,X[n]);

14. 2-Input XOR Gate XOR X Z Y Z = X ^ Y xor(Z,X,Y) X Y Z 0 0 0 0 1 1 X Y Z
Z = X ^ Y
xor(Z,X,Y)
Note:
if Y = 0, Z = X
if Y = 1, Z = ~X
Therefore, an XOR gate can be used
as a controlled inverter

15. Exclusive-NOR Gate XNOR (NOT – XOR)
Behavior:
The output of an XNOR gate is HIGH
only if the number of HIGH inputs is EVEN
assign Z = ~(X[1] ^ X[2] ^ ... ^ X[n]);
assign Z = ~^X;
xnor(Z,X[1],X[2],...,X[n]);

16. 2-Input XNOR Gate XNOR Z = ~(X ^ Y) Z = X ~^ Y xnor(Z,X,Y) X Z Y X Y Z X Z Y
Z = ~(X ^ Y)
Z = X ~^ Y
xnor(Z,X,Y)
Note: Z = 1 if X = Y
Therefore, an XNOR gate can be used
as an equality detector

17. NAND Gate (NOT-AND) Behavior:
The output of an NAND gate is LOW only if all inputs are HIGH
assign Z = ~(X[1] & X[2] & ... & X[n]);
assign Z = ~&X;
nand(Z,X[1],X[2],...,X[n]);

18. NOR Gate (NOT – OR) Behavior:
The output of an NOR gate is HIGH only if all inputs are LOW
assign Z = ~(X[1] | X[2] | ... | X[n]);
assign Z = ~|X;
nor(Z,X[1],X[2],...,X[n]);

19. Gates4.v Verilog gate level primitives Verilog reduction operators
module gates ( X ,Z, Y );
input [4:1] X ;
wire [4:1] X ;
output [6:1] Z ;
wire [6:1] Z ;
output [6:1] Y ;
wire [6:1] Y ;
and(Z[6],X[1],X[2],X[3],X[4]);
nand(Z[5],X[1],X[2],X[3],X[4]);
or(Z[4],X[1],X[2],X[3],X[4]);
nor(Z[3],X[1],X[2],X[3],X[4]);
xor(Z[2],X[1],X[2],X[3],X[4]);
xnor(Z[1],X[1],X[2],X[3],X[4]);
assign Y[6] = &X;
assign Y[5] = ~&X;
assign Y[4] = |X;
assign Y[3] = ~|X;
assign Y[2] = ^X;
assign Y[1] = ~^X;
endmodule
Verilog gate level primitives
Verilog reduction operators

20. and(Z[6],X[1],...
nand(Z[5],X[1], ...
or(Z[4],X[1], ...
nor(Z[3],X[1], ...
xor(Z[2],X[1], ...
xnor(Z[1],X[1], ...
assign Y[6] = &X;
assign Y[5] = ~&X;
assign Y[4] = |X;
assign Y[3] = ~|X;
assign Y[2] = ^X;
assign Y[1] = ~^X;

21. NAND Gate X X Z Z = Y Y Z = ~(X & Y) Z = ~X | ~Y X Y W Z 0 0 0 1
X Y ~X ~Y Z

22. De Morgan’s Theorem-1 ~(X & Y) = ~X | ~Y Change & to | and | to &
NOT all variables
Change & to | and | to &
NOT the result

23. NOR Gate X X Z Z Y Y Z = ~(X | Y) Z = ~X & ~Y X Y Z X Y ~X ~Y Z 0 0 1
X Y ~X ~Y Z

24. De Morgan’s Theorem-2 ~(X | Y) = ~X & ~Y Change & to | and | to &
NOT all variables
Change & to | and | to &
NOT the result

25. Sum of Products Design X Y minterms 0 0 m0 = ~X & ~Y 0 1 m1 = ~X & Y

26. Sum of Products Design Design an XOR gate X Y Z 0 0 0 0 1 1 1 0 1
m1 = ~X & Y
m2 = X & ~Y
Z = m1 | m2
= (~X & Y) | (X & ~Y)

27. Product of Sums Design X Y minterms maxterms
m0 = ~X & ~Y M0 = ~m0 = X | Y
m1 = ~X & Y M1 = ~m1 = X | ~Y
m2 = X & ~Y M2 = ~m2 = ~X | Y
m3 = X & Y M3 = ~m3 = ~X | ~Y

28. Product of Sums Design Design an XOR gate X Y Z 0 0 0 M0 = X | Y 0 1 1
M0 = X | Y
M3 = ~X | ~Y
Z = M0 & M3
= (X | Y) & (~X | ~Y)

29. Venn Diagrams
~X & Y X Y

30. Unity ~X & Y X & Y X Y (X & Y) | (~X & Y) = Y
Dual: (X | Y) & (~X | Y) = Y

31. Absorption-1
X & Y X Y
Y | (X & Y) = Y
Dual: Y & (X | Y) = Y

32. Absorption-2 ~X & Y X Y X | (~X & Y) = X | Y
Dual: X & (~X | Y) = X & Y

33. Distributive Law - a
X | (Y & Z) = (X | Y) & (X | Z)

34. Distributive Law - b
X & (Y | Z) = (X & Y) | (X & Z)

35. Venn Diagrams and Minterms

36. Venn Diagrams and Minterms
XYZ + XYZ + XYZ = XZ + XY

37. Three-variable K-MapsX YZ 00 01 11 10 1 2 3 4 5 6 7 1 1 1 1
F = m0 | m2 | m5 | m7
= S(0,2,5,7)

38. Three-variable K-MapsX YZ 00 01 11 10 1 1 1 1 1
F = X & Z
| ~X & ~Z

39. Three-variable K-MapsX YZ 00 01 11 10 1 1 1 1 1 1 1
F = Y
| ~Z

40. Four-variable K-Maps F(W,X,Y,Z) = S(2,4,5,6,7,9,13,14,15) WX YZ 00 0111 10 1 2 3 4 5 6 7 8 9 12 13 14 15
F(W,X,Y,Z) = S(2,4,5,6,7,9,13,14,15)

41. Four-variable K-Maps YZ 00 01 11 10 WX 00 1 F = ~W & X | X & Y
| ~W & Y & ~Z
| W & ~Y & Z 01 1 1 1 1 11 1 1 1 10 1

42. Four-variable K-Maps YZ 00 01 11 10 WX F = ~W & Z 00 1 1 1 1
| W & X & Y 01 1 1
| ~X & ~Z 11 1 1 10 1 1

43. A 1-Bit Comparator
The variable Gout is 1 if Gin = 1 or if Ein = 1 and x > y.
The variable Eout is 1 if Ein = 1 and x = y.
Gout = Gin | Ein & x & ~y
Eout = Ein & ~x & ~y | Ein & x & y
= Ein & (~x & ~y | x & y)
= Ein & (x ~^ y)

44. module comp4 ( x, y, gt, eq, lt );
input [3:0] x ;
wire [3:0] x ;
input [3:0] y ;
wire [3:0] y ;
output lt ;
wire lt ;
output gt ;
wire gt ;
output eq ;
wire eq ;
A 4-Bit Comparator x y 1 1 1 lt 1

45. Turning on an LED

46. Turning on an LED
This is what
we use in Lab

47. 7-Segment Display

48. 7-Segment Display Truth table D a b c d e f g 0 1 1 1 1 1 1 0
seg7dec
D(3:0)
AtoG(6:0)
Truth table
D a b c d e f g
D a b c d e f g A b C d E F

49. Verilog hex7seg.v a f b g e c d module hex7seg(D,AtoG); input [3:0] D;
output [6:0] AtoG;
reg [6:0] AtoG;
case(D)
0: AtoG = 7'b ;
1: AtoG = 7'b ;
2: AtoG = 7'b ;
3: AtoG = 7'b ;
4: AtoG = 7'b ;
5: AtoG = 7'b ;
6: AtoG = 7'b ;
7: AtoG = 7'b ;
8: AtoG = 7'b ;
9: AtoG = 7'b ;
'hA: AtoG = 7'b ;
'hb: AtoG = 7'b ;
'hC: AtoG = 7'b ;
'hd: AtoG = 7'b ;
'hE: AtoG = 7'b ;
'hF: AtoG = 7'b ;
default: AtoG = 7'b ; // 0
endcase
endmodule
hex7seg.v
Verilog a b c d e f g

50. SW7seg.v Verilog AAtoGG AtoG
// Title : Toggle switches to 7-Segment Display
// Author : R. E. Haskell
module SW7seg(SW,LEDR,AtoG,AAtoGG);
input [7:0] SW;
output [7:0]LEDR;
output [6:0] AtoG;
output [6:0] AAtoGG;
wire [6:0] AtoG;
wire [6:0] AAtoGG;
wire [7:0] LEDR;
assign LEDR = SW;
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));
hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));
endmodule
AAtoGG
AtoG

51. Wiring up the top-level design in Verilog
AAtoGG
AtoG
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));
hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));

52. Wiring up the top-level design in Verilog
AAtoGG
AtoG
hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG));
hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG));

53. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
A multiplexer is a
digital switch
0 0

54. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
0 1

55. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
1 0

56. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
1 1

57. Problem How would you make a Quad 2-to-1 MUX?s
0 A
1 B
Quad
2-to-1
MUX
[A3..A0]
[Y3..Y0]
[B3..B0] s

58. mux.v [A3..A0] [Y3..Y0] [B3..B0] s Quad 2-to-1 MUX
module mux24a(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
reg [3:0] Y;
if(s == 0)
Y = A;
else
Y = B;
endmodule
Quad
2-to-1
MUX
[A3..A0]
[Y3..Y0]
[B3..B0] s

59. module mux24a(A,B,s,Y);
input [3:0] A;
input [3:0] B;
input s;
output [3:0] Y;
reg [3:0] Y;
if(s == 0)
Y = A;
else
Y = B;
endmodule

60. ~S-~R Latch ~S ~R Q ~Q 1 0 0 0 1 1 0 1 1 1 1 Disallowed 1 0 Set
0 0
0 1
1 0
1 1
1 1 Disallowed
1 0 Set
0 1 Reset 1 1
0 1
Store
1 0
Q0 !Q0
X Y nand
0 0 1
0 1 1
1 0 1
1 1 0
To close or lock with or as if with a latch, To catch or fasten

61. S-R Latch module RSlatchNOR ( Q ,R ,S ); input R ; wire R ; input S ;
wire S ;
output Q ;
wire Q ;
wire F1, F2;
nor #10 (F1,F2,R);
nor #10 (F2,F1,S);
assign Q = F1;
endmodule
10ns propagation delay

62. R S Q
0 0 Q0 store
set
reset
disallowed

63. D Latch S ~S ~R R D CLK Q ~Q Note that Q follows D
X 0 Q0 ~Q0
D CLK Q ~Q
Note that Q follows D
when the clock in high,
and is latched when the
clock goes to zero.

64. D Latch module Dlatch ( Q ,EN ,D ); input EN ; wire EN ; input D ;
wire D ;
output Q ;
reg Q ;
or EN)
if(EN == 1)
Q = D;
endmodule
D Latch D EN Q
Q follows D when EN is high, and remains unchanged when EN is low.

65. D Latch

66. D Flip-Flop D gets latched to Q on the rising edge of the clock.
clk D Q !Q
X 0 Q0 !Q0
D clk Q !Q
Positive edge triggered
D gets latched to Q on the rising edge of the clock.
Behavior
clk)
Q <= D;

67. DFFclr.v module DFFclr (D, clk, clr, Q, notQ ); input clk ; wire clk ;
input clr ;
wire clr ;
input D ;
wire D ;
output Q ;
reg Q ;
output notQ ;
wire notQ ;
clk or posedge clr)
if(clr == 1)
Q <= 0;
else
Q <= D;
assign notQ = ~Q;
endmodule
DFFclr.v
Asynchronous clear

68. D Flip-Flop with Asynchronous Clear

69. A 1-Bit Register

70. A 1-Bit Register
If LOAD = 1, then INP0 gets latched to Q0 on the rising edge of the clock, CLK

71. A 4-Bit Register

72. Implementing Registers in Verilog
// A 4-bit register with asynchronous clear and load
module reg4(Clk,Clear,Load,D,Q);
input [3:0] D;
input Clk,Clear,Load;
output [3:0] Q;
reg [3:0] Q;
Clk or posedge Clear)
if(Clear == 1)
Q <= 0;
else if(Load)
Q <= D;
endmodule

73. 4-Bit Shift Register

74. shift4.v Note non-blocking assignment
module ShiftReg(clk,clr,data_in,Q);
input clk;
input clr;
input data_in;
output [3:0] Q;
reg [3:0] Q;
// 4-bit Shift Register
clk or posedge clr)
begin
if(clr == 1)
Q <= 0;
else
Q[3] <= data_in;
Q[2:0] <= Q[3:1];
end
endmodule
Note non-blocking assignment

75. shift4 simulation

76. Ring Counter

77. ring4.v module ring4(clk,clr,Q); input clk; input clr; output [3:0] Q;
reg [3:0] Q;
// 4-bit Ring Counter
clk or posedge clr)
begin
if(clr == 1)
Q <= 1;
else
Q[3] <= Q[0];
Q[2:0] <= Q[3:1];
end
endmodule

78. ring4 simulation

79. Johnson Counter

80. johnson4.v module johnson4(clk,clr,Q); input clk; input clr;
output [3:0] Q;
reg [3:0] Q;
// 4-bit Johnson Counter
clk or posedge clr)
begin
if(clr == 1)
Q <= 0;
else
Q[3] <= ~Q[0];
Q[2:0] <= Q[3:1];
end
endmodule

81. Johnson Counter

82. 3-Bit Counter Behavior clr count3 Q(2 downto 0) clk
clk or posedge clr)
begin
if(clr == 1)
Q <= 0;
else
Q <= Q + 1;
end

83. counter3.v module counter3 (clk, clr, Q ); input clr ; wire clr ;
input clk ;
wire clk ;
output [2:0] Q ;
reg [2:0] Q ;
// 3-bit counter
clk or posedge clr)
begin
if(clr == 1)
Q <= 0;
else
Q <= Q + 1;
end
endmodule
Asynchronous clear
Output count increments
on rising edge of clk

84. counter3 Simulation

85. Recall Divide-by-8 CounterQ0 Q1 Q2 D0 D1 D2 s s s s s s s s
State Q2 Q1 Q D2 D1 D0
Present state Next state
Use Q2, Q1, Q0 as inputs to a combinational circuit
to produce an arbitrary waveform.

86. Example
State Q2 Q1 Q D2 D1 D y Q2
Q1 Q0 00 01 11 10 1 s s s s s s s s
y = ~Q2 & ~Q1
| Q2 & Q0

87. Sequence Detectors Moore machine: Output is a function
of only the state
-- 5 states
output
Mealy machine:
Output is a function
of the state and the
input
-- 4 states

88. Mealy Machine
Note: Output changes
when input changes

89. Mealy Machine