1. CS 252 Graduate Computer Architecture Lecture 2 - Metrics and Pipelining
Krste Asanovic
Electrical Engineering and Computer Sciences
University of California at Berkeley
CS252 S05

2. Review from Last Time Computer Architecture >> instruction sets
Computer Architecture skill sets are different
5 Quantitative principles of design
Quantitative approach to design
Solid interfaces that really work
Technology tracking and anticipation
CS 252 to learn new skills, transition to research
Computer Science at the crossroads from sequential to parallel computing
Salvation requires innovation in many fields, including computer architecture
Opportunity for interesting and timely CS 252 projects exploring CS at the crossroads
RAMP as experimental platform
8/30
CS252-Fall’07
CS252 S05

3. Review (continued) Other fields often borrow ideas from architecture
Quantitative Principles of Design
Take Advantage of Parallelism
Principle of Locality
Focus on the Common Case
Amdahl’s Law
The Processor Performance Equation
Careful, quantitative comparisons
Define, quantity, and summarize relative performance
Define and quantity relative cost
Define and quantity dependability
Define and quantity power
Culture of anticipating and exploiting advances in technology
Culture of well-defined interfaces that are carefully implemented and thoroughly checked
8/30
CS252-Fall’07
CS252 S05

4. Metrics used to Compare Designs
Cost
Die cost and system cost
Execution Time
average and worst-case
Latency vs. Throughput
Energy and Power
Also peak power and peak switching current
Reliability
Resiliency to electrical noise, part failure
Robustness to bad software, operator error
Maintainability
System administration costs
Compatibility
Software costs dominate
8/30
CS252-Fall’07
CS252 S05

5. Architect affects all of these
Cost of Processor
Design cost (Non-recurring Engineering Costs, NRE)
dominated by engineer-years (~$200K per engineer year)
also mask costs (exceeding $1M per spin)
Cost of die
die area
die yield (maturity of manufacturing process, redundancy features)
cost/size of wafers
die cost ~= f(die area^4) with no redundancy
Cost of packaging
number of pins (signal + power/ground pins)
power dissipation
Cost of testing
built-in test features?
logical complexity of design
choice of circuits (minimum clock rates, leakage currents, I/O drivers)
Architect affects all of these
8/30
CS252-Fall’07
CS252 S05

6. System-Level Cost Impacts
Power supply and cooling
Support chipset
Off-chip SRAM/DRAM/ROM
Off-chip peripherals
8/30
CS252-Fall’07
CS252 S05

7. What is Performance? Latency (or response time or execution time)
time to complete one task
Bandwidth (or throughput)
tasks completed per unit time
8/30
CS252-Fall’07
CS252 S05

8. Definition: Performance
Performance is in units of things per sec
bigger is better
If we are primarily concerned with response time
performance(x) = execution_time(x)
" X is n times faster than Y" means
Performance(X) Execution_time(Y)
n = =
Performance(Y) Execution_time(X)
8/30
CS252-Fall’07
CS252 S05

9. Performance Guarantees
Inputs C B A
Execution Rate
Average Rate: A > B > C
Worst-case Rate: A < B < C
8/30
CS252-Fall’07
CS252 S05

10. Types of Benchmark Synthetic Benchmarks Toy Programs Kernels
Designed to have same mix of operations as real workloads, e.g., Dhrystone, Whetstone
Toy Programs
Small, easy to port. Output often known before program is run, e.g., Nqueens, Bubblesort, Towers of Hanoi
Kernels
Common subroutines in real programs, e.g., matrix multiply, FFT, sorting, Livermore Loops, Linpack
Simplified Applications
Extract main computational skeleton of real application to simplify porting, e.g., NAS parallel benchmarks, TPC
Real Applications
Things people actually use their computers for, e.g., car crash simulations, relational databases, Photoshop, Quake
8/30
CS252-Fall’07
CS252 S05

11. Performance: What to measure
Usually rely on benchmarks vs. real workloads
To increase predictability, collections of benchmark applications-- benchmark suites -- are popular
SPECCPU: popular desktop benchmark suite
CPU only, split between integer and floating point programs
SPECint2000 has 12 integer, SPECfp2000 has 14 integer pgms
SPECCPU2006 to be announced Spring 2006
SPECSFS (NFS file server) and SPECWeb (WebServer) added as server benchmarks
Transaction Processing Council measures server performance and cost-performance for databases
TPC-C Complex query for Online Transaction Processing
TPC-H models ad hoc decision support
TPC-W a transactional web benchmark
TPC-App application server and web services benchmark
8/30
CS252-Fall’07
CS252 S05

12. Summarizing Performance
System
Rate (Task 1)
Rate (Task 2) A 10 20 B
Which system is faster?
8/30
CS252-Fall’07
CS252 S05

13. … depends who’s selling
System
Rate (Task 1)
Rate (Task 2) A 10 20 B
Average 15
Average throughput
System
Rate (Task 1)
Rate (Task 2) A
0.50
2.00 B
1.00
Average
1.25
Throughput relative to B
System
Rate (Task 1)
Rate (Task 2) A
1.00 B
2.00
0.50
Average
1.25
Throughput relative to A
8/30
CS252-Fall’07
CS252 S05

14. Summarizing Performance over Set of Benchmark Programs
Arithmetic mean of execution times ti (in seconds)
1/n i ti
Harmonic mean of execution rates ri (MIPS/MFLOPS)
n/ [i (1/ri)]
Both equivalent to workload where each program is run the same number of times
Can add weighting factors to model other workload distributions
8/30
CS252-Fall’07
CS252 S05

15. Normalized Execution Time and Geometric Mean
Measure speedup up relative to reference machine
ratio = tRef/tA
Average time ratios using geometric mean
n(I ratioi )
Insensitive to machine chosen as reference
Insensitive to run time of individual benchmarks
Used by SPEC89, SPEC92, SPEC95, …, SPEC2006
….. But beware that choice of reference machine can suggest what is “normal” performance profile:
8/30
CS252-Fall’07
CS252 S05

16. Vector/Superscalar Speedup
100 MHz Cray J90 vector machine versus 300MHz Alpha 21164
[LANL Computational Physics Codes, Wasserman, ICS’96]
Vector machine peaks on a few codes????
8/30
CS252-Fall’07
CS252 S05

17. Superscalar/Vector Speedup
100 MHz Cray J90 vector machine versus 300MHz Alpha 21164
[LANL Computational Physics Codes, Wasserman, ICS’96]
Scalar machine peaks on one code???
8/30
CS252-Fall’07
CS252 S05

18. How to Mislead with Performance Reports
Select pieces of workload that work well on your design, ignore others
Use unrealistic data set sizes for application (too big or too small)
Report throughput numbers for a latency benchmark
Report latency numbers for a throughput benchmark
Report performance on a kernel and claim it represents an entire application
Use 16-bit fixed-point arithmetic (because it’s fastest on your system) even though application requires 64-bit floating-point arithmetic
Use a less efficient algorithm on the competing machine
Report speedup for an inefficient algorithm (bubblesort)
Compare hand-optimized assembly code with unoptimized C code
Compare your design using next year’s technology against competitor’s year old design (1% performance improvement per week)
Ignore the relative cost of the systems being compared
Report averages and not individual results
Report speedup over unspecified base system, not absolute times
Report efficiency not absolute times
Report MFLOPS not absolute times (use inefficient algorithm)
[ David Bailey “Twelve ways to fool the masses when giving performance results for parallel supercomputers” ]
8/30
CS252-Fall’07
CS252 S05

19. Benchmarking for Future Machines
Variance in performance for parallel architectures is going to be much worse than for serial processors
SPECcpu means only really work across very similar machine configurations
What is a good benchmarking methodology?
Possible CS252 project
Berkeley View Techreport has “Dwarves” as major types of code that must run well (
Can you construct a parallel benchmark methodology from Dwarves?
8/30
CS252-Fall’07
CS252 S05

20. Power and Energy Energy to complete operation (Joules)
Corresponds approximately to battery life
(Battery energy capacity actually depends on rate of discharge)
Peak power dissipation (Watts = Joules/second)
Affects packaging (power and ground pins, thermal design)
di/dt, peak change in supply current (Amps/second)
Affects power supply noise (power and ground pins, decoupling capacitors)
8/30
CS252-Fall’07
CS252 S05

21. Peak Power versus Lower Energy
Peak A
Peak B
Power
Integrate power curve to get energy
Time
System A has higher peak power, but lower total energy
System B has lower peak power, but higher total energy
8/30
CS252-Fall’07
CS252 S05

22. CS252 Administrivia Instructor: Prof. Krste Asanovic
Office: 645 Soda Hall,
Office Hours: M 1-3PM, 645 Soda Hall
T. A.: Rose Liu,
Office Hours: W 4-5PM, 751 Soda Hall
Lectures: Tu/Th, 9:30-11:00AM McLaughlin
Text: Computer Architecture: A Quantitative Approach,
4th Edition (Oct, 2006)
Web page:
Lectures available online <6:00 AM day of lecture
This slide is for the 3-min class administrative matters.
Make sure we update Handout #1 so it is consistent with this slide.
8/30
CS252-Fall’07
CS252 S05

23. CS252 Updates Prereq quiz will cover:
Finite state machines
ISA designs & MIPS assembly code programming (today’s lecture)
Simple pipelining (single-issue, in-order, today’s lecture)
Simple caches (Tuesday’s lecture)
Will try using Bspace this term to manage course private material (readings, assignments) 
Book order late at book store, will try and get you temporary copies of text
This slide is for the 3-min class administrative matters.
Make sure we update Handout #1 so it is consistent with this slide.
8/30
CS252-Fall’07
CS252 S05

24. A "Typical" RISC ISA 32-bit fixed format instruction (3 formats)
32 32-bit GPR (R0 contains zero, DP take pair)
3-address, reg-reg arithmetic instruction
Single address mode for load/store: base + displacement
no indirection
Simple branch conditions
Delayed branch
see: SPARC, MIPS, HP PA-Risc, DEC Alpha, IBM PowerPC,
CDC 6600, CDC 7600, Cray-1, Cray-2, Cray-3
8/30
CS252-Fall’07
CS252 S05

25. Example: MIPS (­ MIPS) Register-Register Op Rs1 Rs2 Rd Opx31 26 25 21 20 16 15 11 10 6 5 Op
Rs1
Rs2 Rd
Opx
Register-Immediate 31 26 25 21 20 16 15
immediate Op
Rs1 Rd
Branch 31 26 25 21 20 16 15
immediate Op
Rs1
Rs2/Opx
Jump / Call 31 26 25
target Op
8/30
CS252-Fall’07
CS252 S05

26. Datapath vs Control
Datapath
Controller
signals
Control Points
Datapath: Storage, FU, interconnect sufficient to perform the desired functions
Inputs are Control Points
Outputs are signals
Controller: State machine to orchestrate operation on the data path
Based on desired function and signals
8/30
CS252-Fall’07
CS252 S05

27. Approaching an ISA Instruction Set Architecture
Defines set of operations, instruction format, hardware supported data types, named storage, addressing modes, sequencing
Meaning of each instruction is described by RTL on architected registers and memory
Given technology constraints assemble adequate datapath
Architected storage mapped to actual storage
Function units to do all the required operations
Possible additional storage (eg. MAR, MBR, …)
Interconnect to move information among regs and FUs
Map each instruction to sequence of RTLs
Collate sequences into symbolic controller state transition diagram (STD)
Lower symbolic STD to control points
Implement controller
8/30
CS252-Fall’07
CS252 S05

28. 5 Steps of MIPS Datapath Figure A.2, Page A-8
Instruction
Fetch
Instr. Decode
Reg. Fetch
Execute
Addr. Calc
Memory
Access
Write
Back
Next PC
MUX 4
Adder
Next SEQ PC
Zero?
RS1
Reg File
Address
MUX
Memory
RS2
ALU
Inst
Memory
Data L M D RD
MUX
MUX
Sign
Extend
IR <= mem[PC];
PC <= PC + 4
Imm
WB Data
Reg[IRrd] <= Reg[IRrs] opIRop Reg[IRrt]
8/30
CS252-Fall’07
CS252 S05

29. 5 Steps of MIPS Datapath Figure A.3, Page A-9
Instruction
Fetch
Instr. Decode
Reg. Fetch
Execute
Addr. Calc
Memory
Access
Write
Back
Next PC
IF/ID
ID/EX
MEM/WB
EX/MEM
MUX
Next SEQ PC
Next SEQ PC 4
Adder
Zero?
RS1
Reg File
Address
Memory
MUX
RS2
ALU
Memory
Data
MUX
MUX
IR <= mem[PC];
PC <= PC + 4
Sign
Extend
Imm
WB Data
A <= Reg[IRrs];
B <= Reg[IRrt] RD RD RD
rslt <= A opIRop B
WB <= rslt
Reg[IRrd] <= WB
8/30
CS252-Fall’07
CS252 S05

30. Inst. Set Processor Controller
IR <= mem[PC];
PC <= PC + 4
Ifetch
JSR
A <= Reg[IRrs];
B <= Reg[IRrt]
opFetch-DCD JR ST
PC <= IRjaddr
if bop(A,b)
PC <= PC+IRim br
jmp
r <= A + IRim
WB <= Mem[r]
Reg[IRrd] <= WB LD
r <= A opIRop IRim
Reg[IRrd] <= WB
WB <= r RI RR
r <= A opIRop B
WB <= r
Reg[IRrd] <= WB
8/30
CS252-Fall’07
CS252 S05

31. 5 Steps of MIPS Datapath Figure A.3, Page A-9
Instruction
Fetch
Instr. Decode
Reg. Fetch
Execute
Addr. Calc
Memory
Access
Write
Back
Next PC
IF/ID
ID/EX
MEM/WB
EX/MEM
MUX
Next SEQ PC
Next SEQ PC 4
Adder
Zero?
RS1
Reg File
Address
Memory
MUX
RS2
ALU
Memory
Data
MUX
MUX
Sign
Extend
Imm
WB Data RD RD RD
Data stationary control
local decode for each instruction phase / pipeline stage
8/30
CS252-Fall’07
CS252 S05

32. Visualizing Pipelining Figure A.2, Page A-8
Time (clock cycles)
Reg
ALU
DMem
Ifetch
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 6
Cycle 7
Cycle 5 I n s t r. O r d e
8/30
CS252-Fall’07
CS252 S05

33. Pipelining is not quite that easy!
Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle
Structural hazards: HW cannot support this combination of instructions (single person to fold and put clothes away)
Data hazards: Instruction depends on result of prior instruction still in the pipeline (missing sock)
Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps).
8/30
CS252-Fall’07
CS252 S05

34. One Memory Port/Structural Hazards Figure A.4, Page A-14
Time (clock cycles)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
ALU I n s t r. O r d e
Load
Ifetch
Reg
DMem
Reg
Reg
ALU
DMem
Ifetch
Instr 1
Reg
ALU
DMem
Ifetch
Instr 2
ALU
Instr 3
Ifetch
Reg
DMem
Reg
Reg
ALU
DMem
Ifetch
Instr 4
8/30
CS252-Fall’07
CS252 S05

35. One Memory Port/Structural Hazards (Similar to Figure A.5, Page A-15)
Time (clock cycles)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
ALU I n s t r. O r d e
Load
Ifetch
Reg
DMem
Reg
Reg
ALU
DMem
Ifetch
Instr 1
Reg
ALU
DMem
Ifetch
Instr 2
Bubble
Stall
Reg
ALU
DMem
Ifetch
Instr 3
How do you “bubble” the pipe?
8/30
CS252-Fall’07
CS252 S05

36. Speed Up Equation for Pipelining
For simple RISC pipeline, CPI = 1:
8/30
CS252-Fall’07
CS252 S05

37. Example: Dual-port vs. Single-port
Machine A: Dual ported memory (“Harvard Architecture”)
Machine B: Single ported memory, but its pipelined implementation has a 1.05 times faster clock rate
Ideal CPI = 1 for both
Loads are 40% of instructions executed
SpeedUpA = Pipeline Depth/(1 + 0) x (clockunpipe/clockpipe)
= Pipeline Depth
SpeedUpB = Pipeline Depth/( x 1) x (clockunpipe/(clockunpipe / 1.05)
= (Pipeline Depth/1.4) x 1.05
= 0.75 x Pipeline Depth
SpeedUpA / SpeedUpB = Pipeline Depth/(0.75 x Pipeline Depth) = 1.33
Machine A is 1.33 times faster
8/30
CS252-Fall’07
CS252 S05

38. Data Hazard on R1 Figure A.6, Page A-17
Time (clock cycles) IF
ID/RF EX
MEM WB I n s t r. O r d e
add r1,r2,r3
sub r4,r1,r3
and r6,r1,r7
or r8,r1,r9
xor r10,r1,r11
Reg
ALU
DMem
Ifetch
8/30
CS252-Fall’07
CS252 S05

39. Three Generic Data Hazards
Read After Write (RAW) InstrJ tries to read operand before InstrI writes it
Caused by a “Dependence” (in compiler nomenclature). This hazard results from an actual need for communication.
I: add r1,r2,r3
J: sub r4,r1,r3
8/30
CS252-Fall’07
CS252 S05

40. Three Generic Data Hazards
Write After Read (WAR) InstrJ writes operand before InstrI reads it
Called an “anti-dependence” by compiler writers. This results from reuse of the name “r1”.
Can’t happen in MIPS 5 stage pipeline because:
All instructions take 5 stages, and
Reads are always in stage 2, and
Writes are always in stage 5
I: sub r4,r1,r3
J: add r1,r2,r3
K: mul r6,r1,r7
8/30
CS252-Fall’07
CS252 S05

41. Three Generic Data Hazards
Write After Write (WAW) InstrJ writes operand before InstrI writes it.
Called an “output dependence” by compiler writers This also results from the reuse of name “r1”.
Can’t happen in MIPS 5 stage pipeline because:
All instructions take 5 stages, and
Writes are always in stage 5
Will see WAR and WAW in more complicated pipes
I: sub r1,r4,r3
J: add r1,r2,r3
K: mul r6,r1,r7
8/30
CS252-Fall’07
CS252 S05

42. Forwarding to Avoid Data Hazard Figure A.7, Page A-19
Time (clock cycles) I n s t r. O r d e
add r1,r2,r3
sub r4,r1,r3
and r6,r1,r7
or r8,r1,r9
xor r10,r1,r11
Reg
ALU
DMem
Ifetch
8/30
CS252-Fall’07
CS252 S05

43. HW Change for Forwarding Figure A.23, Page A-37
ID/EX
EX/MEM
MEM/WR
NextPC
mux
Registers
ALU
Data
Memory
mux
mux
Immediate
What circuit detects and resolves this hazard?
8/30
CS252-Fall’07
CS252 S05

44. Forwarding to Avoid LW-SW Data Hazard Figure A.8, Page A-20
Time (clock cycles) I n s t r. O r d e
add r1,r2,r3
lw r4, 0(r1)
sw r4,12(r1)
or r8,r6,r9
xor r10,r9,r11
Reg
ALU
DMem
Ifetch
8/30
CS252-Fall’07
CS252 S05

45. Data Hazard Even with Forwarding Figure A.9, Page A-21
Time (clock cycles)
Reg
ALU
DMem
Ifetch I n s t r. O r d e
lw r1, 0(r2)
sub r4,r1,r6
and r6,r1,r7
or r8,r1,r9
MIPS actutally didn’t interlecok: MPU without Interlocked Pipelined Stages
8/30
CS252-Fall’07
CS252 S05

46. Data Hazard Even with Forwarding (Similar to Figure A.10, Page A-21)
Time (clock cycles) I n s t r. O r d e
Reg
ALU
DMem
Ifetch
lw r1, 0(r2)
Reg
Ifetch
ALU
DMem
Bubble
sub r4,r1,r6
Ifetch
ALU
DMem
Reg
Bubble
and r6,r1,r7
Bubble
Ifetch
Reg
ALU
DMem
or r8,r1,r9
How is this detected?
8/30
CS252-Fall’07
CS252 S05

47. Software Scheduling to Avoid Load Hazards
Try producing fast code for
a = b + c;
d = e – f;
assuming a, b, c, d ,e, and f in memory.
Slow code:
LW Rb,b
LW Rc,c
ADD Ra,Rb,Rc
SW a,Ra
LW Re,e
LW Rf,f
SUB Rd,Re,Rf
SW d,Rd
Fast code:
LW Rb,b
LW Rc,c
LW Re,e
ADD Ra,Rb,Rc
LW Rf,f
SW a,Ra
SUB Rd,Re,Rf
SW d,Rd
Compiler optimizes for performance. Hardware checks for safety.
8/30
CS252-Fall’07
CS252 S05

48. Control Hazard on Branches Three Stage Stall
Reg
ALU
DMem
Ifetch
10: beq r1,r3,36
14: and r2,r3,r5
18: or r6,r1,r7
22: add r8,r1,r9
36: xor r10,r1,r11
What do you do with the 3 instructions in between?
How do you do it?
Where is the “commit”?
8/30
CS252-Fall’07
CS252 S05

49. Branch Stall Impact
If CPI = 1, 30% branch, Stall 3 cycles => new CPI = 1.9!
Two part solution:
Determine branch taken or not sooner, AND
Compute taken branch address earlier
MIPS branch tests if register = 0 or  0
MIPS Solution:
Move Zero test to ID/RF stage
Adder to calculate new PC in ID/RF stage
1 clock cycle penalty for branch versus 3
8/30
CS252-Fall’07
CS252 S05

50. Pipelined MIPS Datapath Figure A.24, page A-38
Instruction
Fetch
Instr. Decode
Reg. Fetch
Execute
Addr. Calc
Memory
Access
Write
Back
Next PC
Next SEQ PC
ID/EX
EX/MEM
MEM/WB
MUX 4
Adder
IF/ID
Adder
Zero?
RS1
Address
Reg File
Memory
RS2
ALU
Memory
Data
MUX
MUX
Sign
Extend
Imm
WB Data RD RD RD
Interplay of instruction set design and cycle time.
8/30
CS252-Fall’07
CS252 S05

51. Four Branch Hazard Alternatives
#1: Stall until branch direction is clear
#2: Predict Branch Not Taken
Execute successor instructions in sequence
“Squash” instructions in pipeline if branch actually taken
Advantage of late pipeline state update
47% MIPS branches not taken on average
PC+4 already calculated, so use it to get next instruction
#3: Predict Branch Taken
53% MIPS branches taken on average
But haven’t calculated branch target address in MIPS
MIPS still incurs 1 cycle branch penalty
Other machines: branch target known before outcome
8/30
CS252-Fall’07
CS252 S05

52. Four Branch Hazard Alternatives
#4: Delayed Branch
Define branch to take place AFTER a following instruction
branch instruction sequential successor1 sequential successor sequential successorn
branch target if taken
1 slot delay allows proper decision and branch target address in 5 stage pipeline
MIPS uses this
Branch delay of length n
8/30
CS252-Fall’07
CS252 S05

53. Scheduling Branch Delay Slots (Fig A.14)
A. From before branch
B. From branch target
C. From fall through
add $1,$2,$3
if $2=0 then
add $1,$2,$3
if $1=0 then
sub $4,$5,$6
delay slot
delay slot
add $1,$2,$3
if $1=0 then
delay slot
sub $4,$5,$6
becomes
becomes
becomes
if $2=0 then
add $1,$2,$3
add $1,$2,$3
if $1=0 then
sub $4,$5,$6
add $1,$2,$3
if $1=0 then
sub $4,$5,$6
Limitations on delayed-branch scheduling come from 1) restrictions on the instructions that can be moved/copied into the delay slot and 2) limited ability to predict at compile time whether a branch is likely to be taken or not.
In B and C, the use of $1 prevents the add instruction from being moved to the delay slot
In B the sub may need to be copied because it could be reached by another path. B is preferred when the branch is taken with high probability (such as loop branches
A is the best choice, fills delay slot & reduces instruction count (IC)
In B, the sub instruction may need to be copied, increasing IC
In B and C, must be okay to execute sub when branch fails
8/30
CS252-Fall’07
CS252 S05

54. Delayed Branch Compiler effectiveness for single branch delay slot:
Fills about 60% of branch delay slots
About 80% of instructions executed in branch delay slots useful in computation
About 50% (60% x 80%) of slots usefully filled
Delayed Branch downside: As processor go to deeper pipelines and multiple issue, the branch delay grows and need more than one delay slot
Delayed branching has lost popularity compared to more expensive but more flexible dynamic approaches
Growth in available transistors has made dynamic approaches relatively cheaper
8/30
CS252-Fall’07
CS252 S05

55. Evaluating Branch Alternatives
Assume 4% unconditional branch, 6% conditional branch- untaken, 10% conditional branch-taken
Scheduling Branch CPI speedup v. speedup v. scheme penalty unpipelined stall
Stall pipeline
Predict taken
Predict not taken
Delayed branch
8/30
CS252-Fall’07
CS252 S05

56. Problems with Pipelining
Exception: An unusual event happens to an instruction during its execution
Examples: divide by zero, undefined opcode
Interrupt: Hardware signal to switch the processor to a new instruction stream
Example: a sound card interrupts when it needs more audio output samples (an audio “click” happens if it is left waiting)
Problem: It must appear that the exception or interrupt must appear between 2 instructions (Ii and Ii+1)
The effect of all instructions up to and including Ii is totalling complete
No effect of any instruction after Ii can take place
The interrupt (exception) handler either aborts program or restarts at instruction Ii+1
8/30
CS252-Fall’07
CS252 S05

57. Precise Exceptions In-Order Pipelines
Key observation: architected state only change in memory and register write stages.
CS252 S05

58. Summary: Metrics and Pipelining
Machines compared over many metrics
Cost, performance, power, reliability, compatibility, …
Difficult to compare widely differing machines on benchmark suite
Control VIA State Machines and Microprogramming
Just overlap tasks; easy if tasks are independent
Speed Up  Pipeline Depth; if ideal CPI is 1, then:
Hazards limit performance on computers:
Structural: need more HW resources
Data (RAW,WAR,WAW): need forwarding, compiler scheduling
Control: delayed branch, prediction
Exceptions, Interrupts add complexity
Next time: Read Appendix C!
8/30
CS252-Fall’07
CS252 S05