1. NanoPLAs Mike Gregoire

2. Overview ► Similar to CMOS PLA (Programmable Logic Array) ► Uses NOR-NOR logic to implement any logical function ► Like other approaches, macro and micro scale components ► Unlike CMOL, decoders interface micro to macro

3. Technology ► Wires – CNTs and NWs as in other approaches ► Switches – NT-NT junction, apply voltages to change (program) state of junction ► FETs – Using Doped SiNWs electrical fields can be used to gate, preventing conduction ► Stochastic Assembly

4. Architecture ► Build OR plane using the suspended switches ► Problem: No gain, need restoring logic for signal integrity ► Solution: Use SiNW FETs to create NOR plane for restoration

5. Micro-Nano Interface ► Need to be able to program nanowire junctions from microwires ► Use the decoder approach using “2 hot” scheme – faults O(√N) instead of O(N)

6. Defect Tolerance ► Stochastic nanoscale assembly is unreliable ► We don’t care which OR or NOR wires implement the functions as long as some do ► Avoid faults – Similar to DRAM ► Also have spare arrays built into the architecture – Route around faulty arrays

7. Density Gains ► These are best case, do not have best case delay ► Expect 1 or 2 orders of magnitude better density

8. Problems and Issues ► Direct Patterning for decoders is a difficult process (NASIC also has this problem) ► Power Density Issues ► PLA type designs will never be as dense or as fast compared to a custom design like NASIC