1. 1 COMP541 State Machines – 2 Registers and Counters Montek Singh Feb 8, 2007

2. 2Topics  Lab preview  State machine specification styles  Functional: State tables/diagrams/graphs  Structural: Boolean equations  Behavioral: Verilog  Building blocks: registers and counters

3. 3 Lab Preview  Digital lock Recognize sequence of four 4-bit input values Recognize sequence of four 4-bit input values  Input: Use 4 DIP switches on the board Use 4 DIP switches on the board  Output: Indicate ‘yes’/‘no’ on LED display Indicate ‘yes’/‘no’ on LED display  Concepts learned: State machine specification State machine specification State machine synthesis State machine synthesis Generating/measuring time intervals Generating/measuring time intervals Switch button ‘debouncing’ Switch button ‘debouncing’

4. 4 Time intervals module cntr(output out, input clk); reg [31:0] count; reg [31:0] count; always @ (posedge clk) always @ (posedge clk) count <= count + 1; count <= count + 1; assign out = count[22]; assign out = count[22];endmodule What does this do?

5. 5 Button and Debouncing  Button normally high  Mechanical switches can “bounce” Go 1 and 0 a number of times Go 1 and 0 a number of times  We’ll want to Debounce: Any ideas? Debounce: Any ideas? Synchronize with clock Synchronize with clock

6. 6 Flip-Flop for pushbutton module button_test( output q, input btn, input clk ); reg q; always @ (posedge clk) begin if(btn == 1) q <= 1; else q <= 0; endendmodule What does this do?

7. 7 Simple Module to Begin With module led_on(output s6, input button, input clk); wire clkb; //opt cntr C1(clkb, clk); button_test B1(s6, ~button, clkb); endmodule clk to board clock, P88 button to pushbutton, P93 Why ~button? s6 to one of LED segments

8. 8 Things to Think About  Can I press button and not light LED?  What happens if I hold button down for a long time?  What effect will changing period of clkb have? On LED On LED On button debouncing On button debouncing  What does it mean to “press the button”? Think carefully about this Think carefully about this

9. 9 Revisit sequence detector example  Design a state machine to detect the pattern 1101 In last class: We developed state graph for it In last class: We developed state graph for it Today: Learn how to code this in Verilog Today: Learn how to code this in Verilog

10. 10 Verilog Case Statement  Similar to sequence of if/then/else case (expression) case (expression) case: statements; case: statements; other case: statements; other case: statements; default: statements;// optional default: statements;// optional endcase endcase  Example in a moment

11. 11 ‘Parameter’ = defines constant module seq_rec_v(CLK, RESET, X, Z); input CLK, RESET, X; output Z; reg [1:0] state, next_state; parameter A = 2'b00, B = 2'b01, C = 2 'b10, D = 2'b11; Notice that we’ve assigned codes to the states – more later

12. 12 Next State specification always @(X or state) begin case (state) A: if (X == 1) A: if (X == 1) next_state <= B; next_state <= B; else else next_state <= A; next_state <= A; B: if(X) next_state <= C;else next_state <= A; B: if(X) next_state <= C;else next_state <= A; C: if(X) next_state <= C;else next_state <= D; C: if(X) next_state <= C;else next_state <= D; D: if(X) next_state <= B;else next_state <= A; D: if(X) next_state <= B;else next_state <= A;endcase end end The last 3 cases do same thing. Just compact style.

13. 13 On Reset or CLK always @(posedge CLK or posedge RESET) begin if (RESET == 1) state <= A; else state <= next_state; end Notice that state only gets updated on +ve edge of clock (or on reset)

14. 14Output always @(X or state) begincase(state) A: Z <= 0; B: Z <= 0; C: Z <= 0; D: Z <= X ? 1 : 0; endcaseend

15. 15 Pitfall: Beware of Unexpected Latches!  You can easily specify latches unexpectedly Hangover from programming in C…! Hangover from programming in C…!  always will try to synthesize FF: if (select) out <= A; if (!select) out <= B; FF added to save old value if condition is false FF added to save old value if condition is false  To avoid extra FF, cover all possibilities: if (select) out <= A; else out <= B;

16. 16 Comment on Book Code  Could shorten  Don’t need next_state, for example Can just set state on clock Can just set state on clock Note that the two are a little different in function Note that the two are a little different in function  Don’t need three always clauses Although it’s easier to have combinational code to set output be separate Although it’s easier to have combinational code to set output be separate  Template helps synthesizer Check to see whether your state machines were recognized Check to see whether your state machines were recognized

17. 17 Registers and Counters: Definitions  Register – a set of flip-flops May include extensive logic to control state transition May include extensive logic to control state transition  May allow shifting register also refers to fast memory for storing data in a computer register also refers to fast memory for storing data in a computer  Counter Register that goes through sequence of states as it is clocked Register that goes through sequence of states as it is clocked

18. 18 Simple Register  Store D  On posedge of Clock  Clear signal normally high Power-up reset Power-up reset  Symbol

19. 19Clocking  Typically don’t want to load every clock  Can gate the clock But added clock skew is a problem But added clock skew is a problem

20. 20Enable  If load H, then D is gated through  Otherwise, Q is fed back Keep same value Keep same value  No clock gating  Did this because D FF doesn’t have a “no change” behavior

21. 21Counters  Counter is a register – has state  Also goes through sequence of states – counts – on clock or other pulses  Binary counter Counts through binary sequence Counts through binary sequence n bit counter counts from 0 to 2 n n bit counter counts from 0 to 2 n

22. 22 Ripple Counter  Simple  So Q will alternate 1 and 0  Why called ripple counter?

23. 23 Synchronous Counters  Ripple counter is easy  Asynchronous nature may cause problems, though Delay! Delay!  Synchronous counter most common

24. 24 Synchronous Counter  Does have sequence of gates Delay again Delay again

25. 25 Parallel Design  Now constant delay  Can gang these to make long serial-parallel counter

26. 26 Verilog Counter (simple) module count (CLK, EN, Q); input CLK, EN; output [3:0] Q; reg [3:0] Q; always@(posedge CLK) begin if (EN) Q <= Q + 4'b0001; Q <= Q + 4'b0001;endendmodule

27. 27 Verilog Counter (from book) module count_4_r_v (CLK, RESET, EN, Q, CO); input CLK, RESET, EN; output [3:0] Q; output CO; reg [3:0] Q; assign CO = (count == 4'b1111 && EN == 1’b1) ? 1 : 0; always@(posedge CLK or posedge RESET) begin if (RESET) Q <= 4'b0000; Q <= 4'b0000; else if (EN) Q <= Q + 4'b0001; Q <= Q + 4'b0001;endendmodule

28. 28 Arbitrary Count  One more type of counter is useful  Count an arbitrary sequence Maybe you need a sequence of states Maybe you need a sequence of states

29. 29 Circuit and State Diagram

30. 30 Shift Registers  Capability to shift bits In one or both directions In one or both directions  Why? Part of standard CPU instruction set Part of standard CPU instruction set Cheap multiplication Cheap multiplication Serial communications Serial communications  Just a chain of flip-flops

31. 31 Simple 4-Bit Shift Register  Clocked in common  Just serial in and serial out  Is this a FIFO?

32. 32 Parallel Load  Can provide parallel outputs from flip-flops  And also parallel inputs

33. 33Schematic Detail Next

34. 34Detail

35. 35 Why is this useful?  Basis for serial communications  Keyboard  Serial port Initially to connect to terminals Initially to connect to terminals Now mainly for modem Now mainly for modem  USB  Firewire

36. 36Example Clocked 4 times Why do this? Maybe these are far apart Could shift data in, or parallel load What’s on wire at each clock?

37. 37 Table Showing Shift

38. 38 Serial vs. Parallel Transfer  Parallel transfer – over as many wires as word (for example)  Serial transfer – over a single wire Trade time for wires Trade time for wires Takes n times longer Takes n times longer

39. 39 Bidirectional Shift Register  Shift either way  Now we have following possible inputs Parallel load Parallel load Shift from left Shift from left Shift from right Shift from right Also “no change” Also “no change”  Schematic next

40. 40Schematic

41. 41 Verilog for Shift Register module srg_4_r (CLK, SI, Q, SO); input CLK, SI; output [3:0] Q; output SO; reg [3:0] Q; assign SO = Q[3]; always@(posedge CLK) begin Q <= {Q[2:0], SI}; Q <= {Q[2:0], SI};endendmodule

42. 42 Next Time  How to generate a VGA signal  More on state machines

43. 43 Optional Example: One Shot  Help me analyze this one  What does it do?