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EECS 20 Lecture 12 (February 12, 2001) Tom Henzinger Equivalence
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Quiz 1. Draw the transition diagram of the system Delay 0 : [ Nats 0 Bins ] [ Nats 0 Bins ] x [ Nats 0 Bins ], y Nats 0, ( Delay 0 (x)) (y) = 2. Draw the transition diagram of the system 0 if y = 0 x (y-1) if y > 0 { Delay 0
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State before time t : 0 if input at time t-1 was 0, or if t = 0 1 if input at time t-1 was 1
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Delay 0 0 1
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0 1
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0 1 1 / 0 0 / 0
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Delay 0 0 1 1 / 0 0 / 1 1 / 1 0 / 0
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Delay 0 State: ( q1, q2 ) q2q1
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Delay 0 q2q1 0,0 1,0 0,1 1,1
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Delay 0 q2q1 0,0 1,0 0,1 1,1
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Delay 0 q2q1 0,0 1,0 0,1 1,1 1 / 0 0 / 0
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Delay 0 q2q1 0,0 1,0 0,1 1,1 1 / 0 0 / 0 0/00/0 1 / 0
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Delay 0 q2q1 0,0 1,0 0,1 1,1 1 / 0 0 / 0 0/00/0 1 / 0 1/11/1 0 / 1 1 / 1
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Delay 0
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Well-formed !
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Delay 0 Feedback Feedback : [ Nats 0 Unit ] [ Nats 0 Bins ] where Unit = { }.
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Delay 0 Feedback Inputs : Unit Outputs: Bins States: { 0, 1 } initialState = 0 q x output (q,x) nextState (q,x) 0 0 0 1 1 1
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Delay 0 Feedback 0 1 / 0 / 1
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Delay 0 Feedback Only one run ! Time 0 1 2 3 4 5 6 7 Input Output 0 0 0 0 0 0 0 0 State 0 0 0 0 0 0 0 0 0
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Delay 0 Feedback 0 1 / 0 / 1 unreachable
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A state q of a state machine M is unreachable iff q occurs on no run of M ; that is, iff there is no path from the initial state of M to q. Unreachable states can be removed without changing the system (input/output function) implemented by M.
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Delay 0 Feedback 0 / 0
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A more interesting system without inputs Counter Nats 0 Nats 0 0, 1, 2, 3, 4, 5, …
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State-machine implementation of Counter Counter Nats 0 Nats 0 0, 1, 2, 3, 4, 5, … Delay 0 Inc where n Nats 0, inc (n) = n + 1.
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Time 0 1 2 3 4 5 6 7 Input Output 0 1 2 3 4 5 6 7 State 0 1 2 3 4 5 6 7 8 One run Infinitely many states 04321 /0/0 /3/3 /2/2 /1/1
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Yet another system without inputs ModCounter Nats 0 Nats 0 0, 1, 2, 3, 0, 1, 2, … Delay 0 IncMod4 where n Nats 0, incMod4 (n) = ( n + 1 ) mod 4.
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Transition diagram of ModCounter 0321 /0/0 /3/3 /2/2 /1/1
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A discrete-time reactive system can have many different state-machine implementations.
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Two state machines M1 and M2 are equivalent iff they implement the same system (input/output function); that is, iff 1. Inputs [M1] = Inputs [M2], 2. Outputs [M1] = Outputs [M2], and 3. x [ Nats 0 Inputs ], M1 (x) = M2 (x). [ Nats 0 Outputs ]
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Equivalent State Machines 0 1 1/01/0 0/10/1 1/11/10/00/0 M1 a b 1/01/0 0/10/1 1/11/10/00/0 M2
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Equivalent State Machines 0 1 / 0 / 1 M1 0 / 0 M2 2 states 1 state
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Equivalent State Machines 0 1 1/01/0 0/10/1 1/11/10/00/0 M1 0 1 M2 i 1/01/0 0/10/1 1/11/1 0/00/0 0/00/0 1/01/0 3 states 2 states
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Theorem : Two state machines M1 and M2 are equivalent iff there exists a bisimulation between M1 and M2. A binary relation B between States [M1] and States [M2] ; that is, B States [M1] States [M2].
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A binary relation B States [M1] States [M2] is a bisimulation iff 1. ( initialState [M1], initialState [M2] ) B and 2. p States [M1], q States [M2], if ( p, q ) B, then x Inputs [M1], output [M1] ( p, x ) = output [M2] ( q, x ) and ( nextState [M1] ( p, x ), nextState [M2] ( q, x) ) B.
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0 1 1/01/0 0/10/1 1/11/10/00/0 M1 a b 1/01/0 0/10/1 1/11/10/00/0 M2 Bisimulation B = { ( 0, a ), ( 1, b) }
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/ 0 / 1 M1 / 0 M2 Bisimulation B = { ( p 0, q 0 ) } p0p0 q0q0 p1p1
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Bisimulation B = { ( p 0, q i ), ( p 0, q 0 ), ( p 1, q 1 ) } p0p0 1/01/0 0/10/1 1/11/10/00/0 M1 M2 1/01/0 0/10/1 1/11/1 0/00/0 0/00/0 1/01/0 q0q0 q1q1 qiqi p1p1
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Equivalence between state machines: refers only to input and output signals. Bisimulation between state machines: refers to states.
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Why is bisimulation useful ? “Equivalence” says something about infinitely many possible input signals. For finite state machines, “bisimulation” says something about finitely many possible relationships between states. Bisimulation, therefore, is easier to check than equivalence.
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