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Electronic Systems 1 Problem 20: MP3 mapped on NoC-based MPSoC Application Model SDF model (without auto-concurrency) of (modified) MP3 in a certain mode.

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Presentation on theme: "Electronic Systems 1 Problem 20: MP3 mapped on NoC-based MPSoC Application Model SDF model (without auto-concurrency) of (modified) MP3 in a certain mode."— Presentation transcript:

1 Electronic Systems 1 Problem 20: MP3 mapped on NoC-based MPSoC Application Model SDF model (without auto-concurrency) of (modified) MP3 in a certain mode of operation Rates are given by α = 576, β = 36 and γ = 540 tokens All tokens have size of 1 Byte One instance of task types H, S and WB Two instances of task types RQ, RO, AA, HS, FI and SI β γ α H RQ l RQ r RO l RO r S AA l AA r HS l HS r FI l FI r SI l SI r WB α α α α α α α α α α α α α α α β β β β β β β β β β β γ γ γ γ γ γ γ γ γ γ γ

2 Electronic Systems 2 Network-on-chip based Dual Processor Platform Platform Model Platform is battery-powered network-on-chip based dual processor Both processors are here assumed to be of the same type Multi bus is communication resource offering multiple concurrent connections Context memory temporarily stores context of tasks mapped on corresponding processor Buffer memory temporarily stores tokens being transported over active connections Network-on-chip includes multi bus with private buffer memory Processor node includes processor with private context memory Processor node includes multi bus with private buffer memory Battery Processor Node Network On Chip Processor Node Platform Context Memory ProcessorMulti Bus Buffer Memory Processor Node Multi Bus Buffer Memory Network-On Chip

3 Electronic Systems 3 Platform and Mapping Platform Model Memories can always serve requests for reservation of space (bounds to be determined) Multi busses can always serve requests for setting up connection (bounds to be determined) For each exchange of tokens a new connection is set up Connection that is being set up can only become active after fixed set up delay Processors use FCFS scheduling with fixed context switching times Tasks require fixed amount of context memory to enable execution Execution times of tasks are given by independent discrete uniform distributions Memories, processors and multi busses all consume power provided by the same battery Mapping Task is mapped on processor of a node Channel between tasks mapped on same node is mapped on multi bus of that node Channel between tasks mapped on different nodes is mapped on multi bus of network on chip Battery Processor Node Network On Chip Processor Node

4 Electronic Systems 4 Mapping and Profiling Data Task TypeExecution Time Distribution (Cycles)Context Memory Requirement (Bytes) H[311203, 921492]32024 RQ[61271, 1424526]41240 RO[2746, 32081]36421 S[4225, 19164]25452 AA[5030, 13811]29548 HS[514641, 932889]31548 FI[9804, 10566]41010 SI[1469925, 1677594]34575 WB[48119, 49736]29880 TaskHRQ l RQ r RR l RR r SAA l AA r HS l HS r FI l FI r SI l SI r WB Node112122121212122 Mapping Profiling Data

5 Electronic Systems 5 Other Parameters Processor Node Processor frequency1.67·10 8 Hz Context switching time for processor1500 Cycles Power consumption of processor0.084 Watt Bandwidth of each connection provided by multi bus4·10 8 Bytes/Second Latency for setting up connection by multi bus1·10 -4 Second Power consumption of multi bus5·10 -7 Watt/Byte Power consumption of context and buffer memory1·10 -7 Watt/Byte Network-on-Chip Bandwidth of each connection provided by multi bus1·10 8 Bytes/Second Latency for setting up connection by multi bus5·10 -4 Second Power consumption of multi bus2.5·10 -6 Watt/Byte Power consumption of buffer memory2.5·10 -7 Watt/Byte WB Task Should execute 38 times per Second Next deadline = time of starting previous execution + 1/38 Seconds No means to prevent deadline misses included

6 Electronic Systems 6 Performance Metrics Application Throughput of WB task (number of executions per second) Deadline miss probability for WB task Platform Time-average utilization of processors (load) Time-average number of concurrent connections for each multi bus Sum of maximum number of concurrent connections for all multi busses together Time-average occupancy of all memories Maximum occupancy of all memories Nominal power consumption (time-average power consumption) Peak power consumption (maximum power consumption) Special Case Same problem but now with processor node modified to have a single memory for storing both the context of tasks and the tokens being transported

7 Electronic Systems 7 Additional Remarks Full details of application and platform model regarding how resources are claimed, allocated and used are discussed in accompanying pdf document Profiling data and parameter values are somewhat tuned for the example and hence performance results do not reflect a real system Example was developed specifically for hands-on part of tutorials at DSD’05 and FDL’05 Contact B.D.Theelen@tue.nl


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