1. 1 Analog Leaf Cell (ALC) Group Advisor: Prof. David Parent Taslima Rahman Mariavanessa Pascua Siu Kuen Leung Kuang-Wai (Kenneth) Tseng Scott Echols 12/02/2005

2. 2 What is our project??  Designing a teaching environment targeted to all EE students  Implementing Super MOS  Writing up tutorials

3. 3 Outline  Problem  Objective  Skillsets  Block Diagram  Previous Work  Schedule  Resources & Cost  Targeted Audience  Preliminary work  Conclusion

4. 4 Problem  Not all EE students have the hands-on experience of an IC design, fabrication, & testing flow  EE students need to be better prepared to compete for jobs in the global economy  Learning the IC design flow is time consuming

5. 5 Objective  Providing Analog Leaf Cell Environment  Semi-custom design approach for EE124  Reduction of learning and fabrication time  Prepare all EE students  Compete for jobs in a global economy  Require less on the job training

6. 6 Skillsets  The Skills that we need to implement our project  EE129, EE166, AND EE124  EE129 (Introduction to IC Processing)  EE166 (Design of CMOS Digital Integrated Circuit)  EE124 (Microelectronic Design II)

7. 7 Block Diagram Process Steps to Implement our Project DESIGN (State of the art CAD tool) TEST (TEST DEVICES ON WAFER IN FAB LAB) WRITE UP TUTORIALS (SET UP A MINI LAB MANUAL FOR EE124 AND EE129) PROCESS (FABRICATE WAFER IN FAB LAB)

8. 8 Previous Work  1999 no Custom IC resources  From 2001 to 2005-(only selected students)  From 2005 to future-(all EE students)  Fundamental to SJSU EE Students.

9. 9 Schedule

10. 10 Resources and Cost  Resources  Fabrication Lab  Cadence Lab  Advisor – Dr. Parent  Cost  Using Fabrication and Cadence Lab ($100 per hour) FREE!  Mask ($650) FREE!  Dr Parent Advising ($100 per hour) FREE!  Group Working hours ($150 per hour)  Total Cost = $ 0 ??

11. 11 Targeted Audience  All EE Students  Potential EE students, transfer students, high school students

12. 12 Preliminary Work Current Mirror schematic

13. 13 Preliminary Work Super MOS schematic

14. 14 Preliminary Work Current Mirror

15. 15 Preliminary Work Super MOS

16. 16 Conclusion  Several devices will be designed, fabricated, and tested using the ALC template.  Simulations using the Cadence lab will be used to verify correct design flow.  The fabrication lab will be used to manufacture and test the devices.  The devices will be used to aid graduate students for MEMS research and may also lead to further undergraduate projects.