1. 048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion isaac@ee.technion.ac.il http://comnet.technion.ac.il/~isaac/ Scheduling in Input-Queued Switches Uniform Traffic Birkhoff-von Neumann

2. Spring 2006048866 – Packet Switch Architectures2 Where We Are  We introduced IQ switches  We saw that HoL blocking reduces throughput  We got tools from queueing theory to analyze more complex queueing systems

3. Spring 2006048866 – Packet Switch Architectures3 Where We Are  We will now study input-queued switches with VOQs (Virtual Output Queues)  No HoL blocking  But we need good scheduling algorithms to obtain 100% throughput

4. Spring 2006048866 – Packet Switch Architectures4 History 1.[Karol et al., 1987] HoL Blocking: Throughput limited to 58% for Bernoulli IID uniform traffic.

5. Spring 2006048866 – Packet Switch Architectures5 History 2.[Tamir and Frazier, 1988] VOQs: remove HoL blocking, increase throughput

6. Spring 2006048866 – Packet Switch Architectures6 History 3.[Anderson et al., 1993] MSM: analogy to MSM (Maximum Size Matching) in bipartite graph

7. Spring 2006048866 – Packet Switch Architectures7 History 4.[McKeown et al., 1995] MWM: MSM (Maximum Size Matching) does not guarantee 100% throughput. MWM (Maximum Weight Matching) does. 5. [Chuang et al., 1998] CIOQ: IQ can emulate OQ with speedup 2. 6.[Chang et al., 1999] BvN: A schedule implementing a Birkhoff-von Neumann decomposition gets 100% throughput.

8. Spring 2006048866 – Packet Switch Architectures8 History 7.[Leonardi et al., 2000 ; Dai and Prabhakar, 2000] Maximal: IQ can get 100% throughput with speedup 2 using maximal matchings. For instance, WFA [Tamir and Chi, 1993], PIM [Anderson et al., 1993], iSLIP [McKeown et al., 1993]. 8. [Andrews and Zhang, 2001] Network: A network of MWM switches is unstable 9. [Chang et al., 2002] LBR: A Load-Balanced Router provides 100% throughput without scheduling.

9. Spring 2006048866 – Packet Switch Architectures9 Achieving 100% throughput 1. Switch model 2. Uniform traffic  Technique: Uniform schedule (easy) 3. Non-uniform traffic, but known traffic matrix  Technique: Non-uniform schedule (Birkhoff-von Neumann) 4. Unknown traffic matrix  Technique: Lyapunov functions (MWM) 5. Faster scheduling algorithms  Technique: Speedup (maximal matchings)  Technique: Memory and randomization (Tassiulas)  Technique: Twist architecture (buffered crossbar) 6. Accelerate scheduling algorithm  Technique: Pipelining  Technique: Envelopes  Technique: Slicing 7. No scheduling algorithm  Technique: Load-balanced router

10. Spring 2006048866 – Packet Switch Architectures10 Head-of-Line Blocking Blocked!

11. Spring 2006048866 – Packet Switch Architectures11

12. Spring 2006048866 – Packet Switch Architectures12

13. Spring 2006048866 – Packet Switch Architectures13 Virtual Output Queues

14. Spring 2006048866 – Packet Switch Architectures14 Scheduler VOQs VOQs: How Packets Move

15. Spring 2006048866 – Packet Switch Architectures15 Question: do more lanes help?  Answer: it depends on the scheduling Head of Line BlockingVOQs with Bad Scheduling Good Scheduling? Ayalon: depends on traffic matrix…

16. Spring 2006048866 – Packet Switch Architectures16 Basic Switch Model A 1 (n) S(n) N N Q NN (n) A 1N (n) A 11 (n) Q 11 (n) 11 A N (n) A NN (n) A N1 (n) D 1N (n) D 11 (n) D NN (n) D N1 (n)

17. Spring 2006048866 – Packet Switch Architectures17 Notations: Arrivals  A ij (n): packet arrivals at input i for output j at time-slot n  A ij (n) = 0 or 1  ij =E[A ij (n)]: arrival rate   =[ ij ]: traffic matrix  A=[A ij (n)] admissible iff:  For all i,  j ij < 1: no input is oversubscribed  For all j,  i ij < 1: no output is oversubscribed

18. Spring 2006048866 – Packet Switch Architectures18 Notations: Schedule  Q ij (n): queue size of VOQ (i,j)  Q=[Q ij (n)]  S ij (n): whether the schedule connects input i to output j  S ij (n) = 0 or 1  No speedup: each input is connected to at most one output, each output to at most one input  We will assume that each input is connected to exactly one output, and each output to exactly one input  S=[S ij (n)] permutation matrix

19. Spring 2006048866 – Packet Switch Architectures19 Scheduling Algorithm  What it does: determine S(n)  How:  Either using traffic matrix ,  Or, in most cases, using queue sizes Q(n) (because  unknown)  Objective: 100% throughput  So that lines are fully utilized  Secondary objective: minimize packet delays/backlogs

20. Spring 2006048866 – Packet Switch Architectures20 What is “100% throughput”?  Work-conserving scheduler  Definition: If there is one or more packet in the system for an output, then the output is busy.  An output queued switch is work-conserving.  Each output can be modeled as an independent single-server queue.  If  then E[Q ij (n)] < C for some C.  Therefore, we say it achieves “100% throughput”.  For fixed-sized packets, work-conservation also minimizes average packet delay. (Q: What happens when packet sizes vary?)  Non work-conserving scheduler  An input-queued switch is, in general, non work-conserving.  Q: What definitions make sense for “100% throughput”?

21. Spring 2006048866 – Packet Switch Architectures21 Some common definitions of 100% throughput 1. Work-conserving 2. For all n,i,j, Q ij (n) < C, i.e., 3. For all n,i,j, E[Q ij (n)] < C i.e., 4. Departure rate = arrival rate, i.e., weaker We will focus on this definition.

22. Spring 2006048866 – Packet Switch Architectures22 Achieving 100% throughput 1. Switch model 2. Uniform traffic  Technique: Uniform schedule (easy) 3. Non-uniform traffic, but known traffic matrix  Technique: Non-uniform schedule (Birkhoff-von Neumann) 4. Unknown traffic matrix  Technique: Lyapunov functions (MWM) 5. Faster scheduling algorithms  Technique: Speedup (maximal matchings)  Technique: Memory and randomization (Tassiulas)  Technique: Twist architecture (buffered crossbar) 6. Accelerate scheduling algorithm  Technique: Pipelining  Technique: Envelopes  Technique: Slicing 7. No scheduling algorithm  Technique: Load-balanced router

23. Spring 2006048866 – Packet Switch Architectures23 Uniform Traffic  Definition: ij = for all i,j  i.e., all input-output pairs have same traffic rate  Condition for admissible traffic: < 1/N  Example: Bernoulli traffic  =  /N  Arrivals at input i are Bernoulli(  ) and i.i.d.

24. Spring 2006048866 – Packet Switch Architectures24 Algorithms that give 100% throughput for uniform traffic  Nearly all algorithms in literature can give 100% throughput when traffic is uniform  For example:  Uniform cyclic.  Random permutation.  Wait-until-full [simulations].  Maximum size matching (MSM) [simulations].  Maximal size matching (e.g. WFA, PIM, iSLIP) [simulations].

25. Spring 2006048866 – Packet Switch Architectures25 Uniform Cyclic Scheduling A1 B C D 2 3 4 B C D 2 3 4 B C D 2 3 4 A1 A1   Each (i,j) pair is served every N time slots: Geom/D/1 Stable for  < 1

26. Spring 2006048866 – Packet Switch Architectures26 Wait-until-full  We don’t have to do much at all to achieve 100% throughput when arrivals are Bernoulli IID uniform.  For example, simulation suggests that the following algorithm leads to 100% throughput.  Wait-until-full:  If any VOQ is empty, do nothing (i.e. serve no queues).  If no VOQ is empty, pick a random permutation.

27. Spring 2006048866 – Packet Switch Architectures27 Maximum Size Matching (MSM)  Intuition: maximize instantaneous throughput  Simulations suggest 100% throughput for uniform traffic. Q 11 (n)>0 Q N1 (n)>0 Request Graph Bipartite Match Maximum Size Match

28. Spring 2006048866 – Packet Switch Architectures28 Some simple algorithms that achieve 100% throughput Wait until full Maximal Matching Algorithm (iSLIP) MSM Uniform Cyclic

29. Spring 2006048866 – Packet Switch Architectures29 Uniform Random Scheduling  At each time-slot, pick a schedule uar among:  The N cyclic permutations  Or the N! permutations  Then P(S i,j =1) = 1/N  Q: why? A1 B C D 2 3 4 B C D 2 3 4 B C D 2 3 4 A1 A1

30. Spring 2006048866 – Packet Switch Architectures30 Uniform Random Scheduling  We get a Geom/Geom/1 system:  We studied the birth-death chain  We get:  Stable when  < 1  

31. Spring 2006048866 – Packet Switch Architectures31 Achieving 100% throughput 1. Switch model 2. Uniform traffic  Technique: Uniform schedule (easy) 3. Non-uniform traffic, but known traffic matrix  Technique: Non-uniform schedule (Birkhoff-von Neumann) 4. Unknown traffic matrix  Technique: Lyapunov functions (MWM) 5. Faster scheduling algorithms  Technique: Speedup (maximal matchings)  Technique: Memory and randomization (Tassiulas)  Technique: Twist architecture (buffered crossbar) 6. Accelerate scheduling algorithm  Technique: Pipelining  Technique: Envelopes  Technique: Slicing 7. No scheduling algorithm  Technique: Load-balanced router

32. Spring 2006048866 – Packet Switch Architectures32 Non-Uniform Traffic  Assume the traffic matrix is:   is admissible  … and non-uniform

33. Spring 2006048866 – Packet Switch Architectures33 Uniform Schedule?  What if uniform schedule?  Each VOQ serviced at rate  = 1/N = 1/4  But arrivals to VOQ(1,2) have rate 12 = 0.57  Birth-death chain with birth rate > death rate  switch unstable!  Need to adapt schedule to traffic matrix

34. Spring 2006048866 – Packet Switch Architectures34 Example 1: (Trivial) scheduling to achieve 100% throughput  Assume we know the traffic matrix, it is admissible, and it follows a permutation:  Then we can simply choose:

35. Spring 2006048866 – Packet Switch Architectures35  Assume we know the traffic matrix, and it doesn’t follow a permutation. For example:  Then we can choose the sequence of service permutations:  And either cycle though it or pick randomly  In general, if we know an admissible , can we pick a sequence S(n) so that  ? Example 2

36. Spring 2006048866 – Packet Switch Architectures36 Doubly Stochastic Matrices   is admissible, or “doubly (strictly) sub- stochastic”  Theorem 1 (von Neumann): There exists  ’={ ij ’} such that  <  ’ and  ’ is doubly stochastic:  i ij =  j ij = 1  Example:

37. Spring 2006048866 – Packet Switch Architectures37 Doubly Stochastic Matrices  Fact 1: the set of doubly stochastic matrices is convex, compact, in R n  Fact 2: any convex, compact set in R n has extreme points, and is equal to the convex hull of its extreme points (Krein-Milman Theorem)

38. Spring 2006048866 – Packet Switch Architectures38 Doubly Stochastic Matrices  Theorem 2 (Birkhoff): Permutation matrices are the extreme points of the set of doubly stochastic matrices  In other words: Given  ’, there exists K numbers  k >0 and K permutation matrices P k such that  Further, K · N 2 -2N+2.

39. Spring 2006048866 – Packet Switch Architectures39 Birkhoff-von Neumann (BvN) Scheduling  BvN decomposition:    ’  {  k, P k }  BvN weighted random scheduling: pick P k with proba.  k  Theorem: BvN scheduling achieves 100% throughput

40. Spring 2006048866 – Packet Switch Architectures40 BvN and 100% Throughput  Proof:  Lindley’s equation:  Birth-death chain  Birth rate: P(A ij (n)=1)=E[A ij (n)]= ij  Death rate:  Birth rate < death rate  100% throughput (“ergodic”)