1. [M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Nov. 11 Overall Project Objective : Dynamic Control The Traffic Lights

2. Status  Design Proposal  Chip Architecture  Behavioral Verilog Implementation  Size estimates  Floorplanning  Behavioral Verilog simulated  Gate Level Design  Component Layout/Simulation  Chip Layout  Complete Simulation

3. Data Input Initial Values Clock Operation T, Left-Turn Counter R, r, R_ L, r_ l Flow Control FSM Light Contro l FSM Selection

4. Old Version

5. Current Version

6. Arithmetic Unit Update  Status – 95%  Array Multiplier-100%  LVS + DRC clean  RCA Adder-100%  LVS + DRC clean  Simulations + finishing touches-0%  Analog Simulations with extractedRC fail  Last interconnects will be added when simulations are run and no buffers or changes need to be made

7. Arithmetic Unit Layout

8. Tom’s FSM  It’s messy, but it passes DRC and LVS  It could be smaller, so I will work to compress it more  No simulations yet

9. Tom’s FSM

10. Most Outputs Other Outputs Inputs

11. Light Control FSM Here is the log file shows where the error is.

12. Light Control FSM However, I found the transistor to check the parameter of it. It is different from what is presented in log file.

13. Light Control FSM  Found a fatal error when doing extracted RC simulations.  Still don’t know how to fix it.

14. Question ?