1. The Multicycle Processor CPSC 321 Andreas Klappenecker

2. Administrative Issues Midterm is on October 12 Allen Parish’s help session Friday 10:15-12:15 Project 1 has been release – work in a team

3. Questions? Problems?

4. Today’s Menu The Multicycle Processor

5. Recall: Marrying two Datapaths What kind of instructions can be realized by these datapaths?

6. Datapaths for Instruction Fetch, Memory and R-type Instructions xtend ALU result Zero ALU Address RegWrite ALU operation 3 MemRead MemWrite ALUSrc MemtoReg xtend ALU result Zero ALU Address RegWrite ALU operation 3 MemRead MemWrite ALUSrc MemtoReg xtend ALU result Zero ALU Address RegWrite ALU operation 3 MemRead MemWrite ALUSrc MemtoReg Note the added multiplexor switching between register 2 and sign-extended immediate value

7. Datapath for MIPS instructions

8. Control We get the control signals from bits 31-26 and 5-0

9. Single memory unit for instructions and data Single arithmetic-logical unit Registers after every major unit (some visible to the programmer, some not) hold output of that unit until value is used in next clock cycle data used in subsequent instructions must be stored in programmer visible registers Multicycle Approach

10. Multicycle Datapath

11. Additional ‘Internal’ Registers Instruction and memory data register both memory and instruction registers are used because both values are needed A and B registers hold register operands ALUout register holds output of ALU

12. Instruction Fetch Instruction Decode and Register Fetch Execution, Memory Address Computation, or Branch Completion Memory Access or R-type instruction completion Write-back step INSTRUCTIONS TAKE FROM 3 - 5 CYCLES! Five Execution Steps

13. Use PC to get instruction and put it in the Instruction Register. PC = PC + 4 RTL "Register-Transfer Language" IR = Memory[PC]; PC = PC + 4; What is the advantage of updating the PC now? Step 1: Instruction Fetch

14. Read registers rs and rt in case we need them Compute the branch address in case the instruction is a branch RTL A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC+(sign-extended(IR[15-0])<<2); No control lines based on the instruction type are set b/c control logic busy "decoding". Step 2: Instruction Decode and Register Fetch

15. ALU performs one of three functions, based on instruction type Memory Reference ALUOut=A+sign-extend(IR[15-0]); R-type ALUOut = A op B; Branch if (A==B) PC = ALUOut; Step 3 (Instruction Dependent)

16. Loads and stores access memory MDR = Memory[ALUOut]; orMemory[ALUOut] = B; R-type instructions finish Reg[IR[15-11]] = ALUOut; The write actually takes place at the end of the cycle on the edge Step 4 (R-type or memory-access)

17. Load operations Reg[IR[20-16]]= MDR; What about all the other instructions? Step 5: Write-back step

18. Summary

19. Clock Cycles per Instruction R-type 4 clock cycles Memory reference instructions 5 clock cycles Branches 3 clock cycles Jumps 3 clock cycles

20. How many cycles will it take to execute this code? lw $t2, 0($t3) lw $t3, 4($t3) beq $t2, $t3, Label#assume not add $t5, $t2, $t3 sw $t5, 8($t3) Label:... What is going on during the 8th cycle of execution? In what cycle does the actual addition of $t2 and $t3 takes place? Questions

21. MIPS Multicycle Datapath Incomplete (branch and jumps…)

22. Control What are the control signals? Finite state machine control Instruction fetch instruction decode memory reference R-type branch jump

23. Multicycle Datapath and Control Lines

25. Outlook What happens precisely during each step of fetch/decode/execute cycles Construct the finite state control machine High-level view

26. Instruction Fetch/Decode/Execute

32. Finite State Machines

33. Instruction Fetch & Decode FSM

34. Memory-Reference FSM Address calculation Load sequence read from memory store to register Access memory Store sequence write

35. R-type Instruction Execution of instruction Completion of instruction

36. Branch Instruction

37. Implementation of FSM A FSM can be implemented by a register holding the state and a block of combinatorial logic Task of the combinatorial logic: Assert appropriate signals Generate the new state to be stored in the register