1. Uli Schäfer JEM Status and plans Algorithms Hardware JEM0, JEM1 Tests Plans

2. Uli Schäfer Algorithms (RTDP) JEP : receive transverse energy pre-sums from Pre- processor (32×32 bins in η×φ, plus overlap in φ) and calculate total and missing transverse energy sums. Find and count jets.  32 JEMs in 2 crates, 4 merger modules. Send trigger bits to central trigger processor. JEM: Receive energies 4×8 ×(e,h) plus overlap (total 88 ch) Synchronisation, parity, mask, threshold Generate jet elements (E e +E h ) Send jet elements to jet algorithm (@80Mb/s) From jet elements (E t ) calculate E x and E y by multiplying cosφ sinφ Sum E x, E y and E t Quad-linear encoding of energies Saturation (4TeV), parity

3. Uli Schäfer Hardware: JEM0 88 de-serialisers : DS92LV1224 11 Input Processors : XC2S200 Main Processor XCV600E/1600E Status: flash configuration and DCS/CAN never implemented. JEM0.0 : incomplete, no use. JEM0.1 : one connector broken (repair in November?), main processor too small to carry jet algorithm. JEM0.2 : fully working, ready for jet tests

4. Uli Schäfer JEM0.0 -top view- Main Input proc. Deser. terminator 15 20 15

5. Uli Schäfer Hardware : JEM1 16 x 6-channel de-serialisers : SCAN921260 on 4 Input daughter modules w. XC2V1500 Jet and Sum Processors XC2V2000 (BF package). Configuration : SystemACE Status: Input daughters: 8 PCBs done, 1 assembled, tests due soon. Main board schematic capture 70%, layout 40% finished. Bruno will take up work on Monday 88 pair

6. Uli Schäfer Input Module top view Module size: 73x76mm 100R differential connectors for LVDS Connector (Bottom) Input Processor 6-ch deser. LVDS diff. FIO Jet Sum Control

7. Uli Schäfer JEM1 components : Input module saga Design complete by end of March Design files to manufacturer: April 2nd PCB production failed First try: misalignment of layers Second try : copper plating insufficient : 5μm on inner layer Third try : via plating insufficient : 13μm >> Submitted to Rohde & Schwarz in July for both PCB production and assembly Successfully produced and delivered end August. No tests yet due to B/Scan software issue. New software acquired and installed.

8. Uli Schäfer JEM1 main board JEM main board mainly consists of Backplane and daughter connectors (TTC, input) Bus drivers (VME) and ECL line drivers/receivers Jet and Sum processors (BGA 1.28mm pitch) G-links. Opto trasnsmitters One large CPLD SystemACE configurator Voltage converters Front panel connectors/LEDs

9. Uli Schäfer Firmware / test For JEM1 some modifications are required, mainly in I/O stages (DDR registers), block RAM, DLLs, hardware multipliers, clock mirror, FCAL handling, E x /E y calculation on input processor, separate sum processor, VME access. Change of channel count per input processor Work started : complete re-write of input processor, since previous version was hard-wired for 8 channels, instantiations, no loops.  Coherent code for both JEM0 and JEM1  debug on JEM0 and hope for plug and play once JEM1 arrives VME register map completely refurbished  adapt on-line software ! Separate test bench w. Windows PC, JEM0.1, configuration via JTAG, data transmission through printer port. Use this test setup for early tests of JEM1 input processor (Andrey)

10. Uli Schäfer Plans / to do Hardware (Bruno/ Uli ): Boundary Scan of input daughter Input processor test module Finish JEM1 design and submit All to be done by end 2003, pay from 2003 CORE money! Firmware (Uli): Complete JEM1 compatible firmware (stable Jan. 2004?) Software: (Cano, Andrey, Thomas) adapt to JEM1 (?) Look into PVSS / OPC /CAN (not CANopen!) (Andrey) ?? Tests (All) Mainz remote jet test in November? RAL test in November? –ROD tests –CMM tests –Full jet code tests (2 JEMs ? Need re-work!) Input daughter test (Andrey)