1. 1 Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing Aids and VOIP. TEAM W3: Digital Voice Processor 525 Jarrett Avery (W3-1) Sean Baker (W3-2) Huiyi Lim (W3-3) Sherif Morcos (W3-4) Amar Sharma (W3-5) Date: 4/26/2006 Short Presentation Design Manager: Abhishek Jajoo

2. 2 Final Presentation Agenda  Title Page  Status  Project Description  Marketing  Algorithm  Implementation/Design Process  Floorplan Evolution  Verification  Digital  Analog  Issues  Layout  Specifications  Conclusions

3. 3Status  Project chosen: 16 bit Delta-Sigma ADC - Basic specs defined  Architecture  Schematic  Floor Planning  Revised Layout Dimensions  Layout Progress  Top Level Analog  Low Pass Filter – DRC, LVS, Simulated  Delta Sigma Modulator – DRC, Simulated  Top Level Digital  PII – DRC, LVS, Simulated  Sinc Filter – DRC, LVS, Simulated  Clock Divider – DRC, LVS, Simulated  Simulation / Verification  All Digital Modules Verified  All Analog Modules Verified  Overall/Top Verified  Optimized Layout  PII Function  Sinc Filter  Analog Side

4. 4 Project Description  What our project does…  Applications  Voice over IP  Hearing aids  Why Delta Sigma modulator 2-3 Slides

5. 5Marketing  Why choose our product over others…  More uses  Superior features of our chip  Low power  Low area  Mixed signal 1-2 Slides

6. 6Algorithm  Overall Block Diagram  Overall Schematic 2 Slides

7. 7Implementation  How the design process evolved  Bit choices (18-bit to 24-bit to 16-bit)  Governing equations  Design decisions 2-3 Slides

8. 8Floorplan  Show how the floorplan changed and evolved  Preliminary Plan -> Final top level 2-3 Slides

9. 9 Digital Verification  Behavioral Verilog – testbench  Structural Verilog – testbench  Simulation outputs showing good output  Schematic (components and top-level module)  Layout (components)  Full-chip (extractedRC) 4-5 Slides (Very Important)

10. Analog Verification

11. 11Issues  Mixed Signal is a bitch  Other problems encountered 1 Slide

12. 12Layout  All components  Mask layers  Overall chip  Add dimensions and floorplan 6-7 Slides

13. 13Specifications  Pin specs – # of pins, input/output  Part specs – component transistor counts, area, density  Chip specs – total transistor count, area, density 3-5 Slides

14. 14Conclusion  Gimme my money 1 Slide Overall 35- 50 Slides