1. 1 A Method for Fast Delay/Area Estimation EE219b Semester Project Mike Sheets May 16, 2000

2. 2 Overview Problem statement Problem statement Proposed solution Proposed solution –Constant delay paradigm –Zero-slack algorithm Implementation Implementation –Incorporation into SIS –Library characterization –Results Conclusions Conclusions Future Work Future Work

3. 3 Problem Statement Given a boolean network, estimate the area if implemented with particular required time constraints Given a boolean network, estimate the area if implemented with particular required time constraints –Estimation should be fast and reasonably accurate Examine how technology independent logic optimization affects the estimation Examine how technology independent logic optimization affects the estimation

4. 4 Area/Delay Models Constant area (traditional) model Constant area (traditional) model –Composed of discretely sized gates with constant area –Mapping involves calculating delay as a function of load Constant delay model Constant delay model –Composed of mathematical functions relating area to size –Mapping involves calculating size (area) as a function of load ND2X1 Area = constant from library Size = constant from library Delay = d int + k*C L Constant Area Model CLCL ND2 Area = A int + A slope *size Size = k*C L /(Delay – d int ) Delay = constant Constant Delay Model CLCL

5. 5 Zero Slack Algorithm Given input arrival times {ai} and output required time {rk}, assign gate delays as follows: 1.Initialize all internal required/arrival times to “unknown” 2.Select the path(s) with the minimum value of (rk-ai)/lp where lp is the length of the path in number of gates 1.For each node from primary inputs to primary outputs 1. Calculate all the (ai, li) pairs from all fanin edges 2. Discard dominated pairs, save the union of the undominated pairs 2.When all primary outputs are reached, calculate minimum (rk-ai)/lp 3.Assign delay of each gate in the selected path(s) to this minimum 4.Update arrival and required times for all fi and fo edges of newly assigned delays 5.Repeat steps 2-4 until all gates are assigned delays n1 n2 n n3 n4 a1 a2 r3 r4 l4 l3 l2 l1 Pair (ai, li) dominates (aj, lj) if ai  aj and li  lj If either (a1, l1) or (a2, l2) dominates the other, the four possible paths through n can be reduced to two, since the dominated path is “faster” than necessary. Pair domination defined:

6. 6 Faster Approximation Select an allowable slack threshold s thresh (if zero then algorithm yields same result as previous) 1.Compute the forward level l j and arrival time a j of all nodes in network using a forward trace 2.Compute the reverse level k j and required time r j of all nodes in network using a backward trace 3.Update the delay of every node as d j = d j + (r j -a j )/(l j +k j ) 4.While the slack of any node exceeds s thresh then repeat steps 1-3.

7. 7 Incorporation into SIS read_library Tech. lib. Manual analysis Est. lib. read_estim BLIF net. read_blif Tech. independent optimization: script.algebraic, script.boolean, etc Tech. dependent optimization: map Fast delay/area estimation: estimate Area Area/delay tradeoff curve

8. 8 Library Characterization Commercial standard cell library have possibly multiple gates that implement the same equation Commercial standard cell library have possibly multiple gates that implement the same equation Each gate in the library has characteristics: Each gate in the library has characteristics: –Size –Delays from all input pins to the output pin for all transitions and several loads –Capacitance for all input pins –Maximum load –Area We need estimation parameters for each class of gates (ie. gates with the same equation): We need estimation parameters for each class of gates (ie. gates with the same equation): –Intrinsic gate delay (d int ) –Drive factor (k) –Area line y-intercept (A int ) –Area line slope (A slope ) –Input capacitance line y-intercept (c int ) –Input capacitance line slope (c slope )

9. 9 Inverter Characterization (1) Inverter delay scales linearly with load/size Inverter delay scales linearly with load/size –Slope is k –Y-intercept is d int

10. 10 Inverter Characterization (2) Inverter area scales linearly with size Inverter area scales linearly with size –Slope is A slope –Y-intercept is A int

11. 11 Characterization Issues Requires at least two gates per class in the library Requires at least two gates per class in the library Additionally, some gates have poor accuracy (trend lines have poor coefficients of determination) Additionally, some gates have poor accuracy (trend lines have poor coefficients of determination) Further research shows the reason is CMOS implementation (below) Further research shows the reason is CMOS implementation (below) Future work might replace linear model with piece-wise linear model for more accuracy Future work might replace linear model with piece-wise linear model for more accuracy NAND-gate CMOS schematic for smaller sizes NAND-gate CMOS schematic for larger sizes

12. 12 Estimation Library These issues are evident in the table These issues are evident in the table –OAI31 and OAI32 have Aslope of 0.0, meaning that the two cells in the library had the same area –NOR3, NOR4 had poor coefficients of determination –Many gates in the library had only one size

13. 13 Estimation Modes Sweep mode Sweep mode –User specifies a range of required times to sweep (possibly only one) and a step size –Estimation starts with the largest required time and steps down until network fails the zero slack algorithm (ie. negative slack is encountered) Binary search mode Binary search mode –Used to find the minimum possible required time (period) given infinite area –Starts at a user-specified maximum and performs a binary search until a pass limit is reached

14. 14 Experimentation Various sized combinational logic benchmarks Various sized combinational logic benchmarks –MCNC c17, c880, c1908, c3540 Various sized sequential logic benchmarks Various sized sequential logic benchmarks –Interpretation of required time is clock period (assuming all flip-flops are clocked synchronously) –MCNC s713, s838, s953, s1196, s1238, s1423 Tested four scripts Tested four scripts –script.none (no optimization), script.algebraic, script.boolean, script.rugged

15. 15 Tradeoff Curves Sweep mode allows multiple required times (clock periods) to be easily tabulated Sweep mode allows multiple required times (clock periods) to be easily tabulated

16. 16 Sensitivity to Optimization Script When delay is non-critical (ie. as required time approaches infinity) When delay is non-critical (ie. as required time approaches infinity) –Area within 20% of no optimization –Variation between optimization scripts mostly under 10%

17. 17 Conclusions Sometimes more optimization yields worse results Sometimes more optimization yields worse results As required times become smaller, more paths become critical requiring larger sizes (area) As required times become smaller, more paths become critical requiring larger sizes (area) –Area increases quickly before failure From the benchmarks shown, estimation is relatively insensitive to technology independent optimization with infinite required times From the benchmarks shown, estimation is relatively insensitive to technology independent optimization with infinite required times

18. 18 Possible Future Work Accuracy Accuracy –Relate estimated areas to actual areas from a good mapping using the full technology library –Use more complex delay equations to handle different rise/fall times –Modify the algorithm to handle the case where a primary input cannot drive the required load Characterization Characterization –Revise characterization to support piece-wise linear functional forms –Automate process so only the actual technology library is required as an input Mapping Mapping –Examine how various mapping options affect estimation –Use buffered fanout trees (Touati) after sizing gates Speed Speed –Compare speed of total estimation procedure to traditional flow Power estimation Power estimation