1. Nanoscale memory cell based on a nanoelectromechanical switched capacitor EECS Min Hee Cho

2. Outline I Introduction Agenda DRAM & Key idea Capacitor type Carbon Nanotube II Mechanical switched capacitor Fabrication SEM image Operation Switching characteristics J. E. Jang, et al. nature nanotechnology 2008 (Samsung Advanced Institute of Technology & U of Cambridge ) J. E. Jang, et al. APPLIED PHYSICS LETTERS 2008 III Low voltage drive Low Gate Voltage Fabrication SEM image IV Summary Summary : Merits Summary : remaining obstacles V References/ Q&A

3. Outline I Introduction Agenda DRAM & Key idea Capacitor structure Carbon Nanotube II Mechanical switched capacitor Fabrication SEM image Operation Switching characteristics III Low voltage drive Low Gate Voltage Fabrication SEM image IV Summary Summary : Merits Summary : remaining obstacles V References/ Q&A

4. Agenda Conventional DRAMNew DRAM FabricationTop-Down processBottom-Up Process (CNT) OperationField Effect Transistor + Capacitor Electromechanical switch + Capacitor Nanoscale memory cell = DRAM with Carbon nanotube

5. DRAM & Key idea Schematic drawing of original designs of DRAM patented in 1968. * Development of DRAM : Cell size is smaller and smaller  TR : On/Off ratio ↓(due to Short channel effect)  Cap : Area of capacitor is also reduced ( Capacitor should be larger to improve performance) * Solution  TR : Mechanical switched TR  Cap: Vertical structure ( increase area of capacitor ) or High K Gate Drain Source Capacitor

7. Trench type Capacitor structure Cylinder type like “HAT” Dielectric :small area

8. Gate Drain Source Capacitor SourceDrain Gate DRAM has several limits as shrinkage * Transistor - low Subthreshold swing (low On/Off ratio) - short channel effect (Off leakage) New challenge for DRAM with CNT * Transistor - Use Electromechanical property not Field effect  On/Off ratio ↑ - Smaller cell area : due to the vertical structure * Additionally, they can use existing silicon technology Area also reduced Conventional DRAM structure New DRAM structure New DRAM structure

9. Carbon Nanotube (CNT) Properties Single WalledCarbon Nanotube (SWNT) Multi-Walled Carbon Nanotube (MWNT) Comparison Diameter (nm)1.2~35~100 Hair (70~100)×10 3 Tension (GPa)~45<50~300 Stainless steel : 0.65~1) Density(g/cc)1.33~1.40-Al ~2.7 Electric resistance (Ω·m) 10×10 -6 5.1×10 -8 Cu 1.7×10 -8 Current density (A/m 2 ) ~109-Cu 106 Thermal conductivity( W/m·K) ~6000~3000 Diamond : 2000~40000, Cu: 393.7 They use CNT as electromechanical materials rather than semiconductor material

10. Outline I Introduction Agenda DRAM & Key idea Capacitor type Carbon Nanotube II Mechanical switched capacitor Fabrication SEM image Operation Switching characteristics III Low voltage drive Low Gate Voltage Fabrication SEM image IV Summary Summary : Merits Summary : remaining obstacles V References/ Q&A

11. Fabrication 0. Make Nb catalyst dot on Substrate I. C 2 H 2 &NH 3 gas 600~650 o C by PECVD : CNT II. Si 3 N 4 (dielectric & insulator) by PECVD III. Cr by sputtering : upper electrode IV. Si 3 N 4 at Drain removed by wet etching  Si 3 N 4 remaining at bottom of MWCNT strengthen the interface  enhance working reliability

12. SEM image

13. * Total cell: 40,000 ea * MWCNT success rate : 95% * Final cell success rate : 50% (failure due to mainly M/A in litho) CNT diameter : 70nm Gap between CNT : 100nm Length : 3.5um Si 3 N 4 thickness : 40nm For single capacitance: 1.05fF SEM images

14. Outline I Introduction Agenda DRAM & Key idea Capacitor type Carbon Nanotube II Mechanical switched capacitor Fabrication SEM image Operation Switching characteristics III Low voltage drive Low Gate Voltage Fabrication SEM image IV Summary Summary : Merits Summary : remaining obstacles V References/ Q&A

15. Write Operation The mutual repulsion between the positive charges on the capacitor and the nanotube in cell 1 prevents the nanotube from making contact with the capacitor, so no current flows, unlike the situation in cell 2, where the nanotube does make contact with the cell. Read Write BL of Cell 1 and  apply 0.1V  gate voltage to the 15V  CNT of Cell 1 begins to bend  contacts  charges flow from CNT(BL) to capacitor

16. * When gate voltage is higher than Vt, Transistor turns on * Vd increase  Vt decreases due to electrostatic force Threshold gate voltage (Vt) OFF ONON Very High gate voltage : Usually DRAM operates at ~1.3V (or less than 2.5V) Switching characteristics

17. Outline I Introduction Agenda DRAM & Key idea Capacitor type Carbon Nanotube II Mechanical switched capacitor Fabrication SEM image Operation Switching characteristics III Low voltage drive Low Gate Voltage Fabrication SEM image IV Summary Summary : Merits Summary : remaining obstacles V References/ Q&A J. E. Jang, et al. APPLIED PHYSICS LETTERS 2008

18. Low Gate Voltage Too high operating voltage (15~20V) APPLIED PHYSICS LETTERS 93, 113105 2008 ∵ The simple planar gate structure imparts a very small electrostatic force to the drain  electrostatic force ∝ 1/d 2  Need high voltage Vertical gate structure In this work They make vertical gate and tie it with drain

19. 14~15V 4~5 V

20. PolyMethyl MethAcrylate (PMMA) : thermoplastic and transparent plastic. PMMA coating after the CNT growth pr ocess. 30 nm SiNx deposition by PECV D E-beam lithography with substrate tilting Cr layer deposition lift-off process (Cr on PMMA removed) 400 nm PMMA coating and ashing process to remove the Thin PMMA on the vertical CNT and gate structure Fabrication

21. 1> Operating Gate voltage can be reduced2> Area also reduced SEM images

22. Outline I Introduction Agenda DRAM Memory Basic Operation Capacitor type Carbon Nanotube II Mechanical switched capacitor Fabrication SEM image Operation Switching characteristics III Low voltage drive Low Gate Voltage Fabrication SEM image IV Summary Summary : Merits Summary : remaining obstacles V References/ Q&A

23. Summary : Merits Excellent ‘ON–OFF’ ratio – Due to the mechanical switching approach  No ultra-shallow n- or p-type junctions  No thin-gate dielectrics Compatible with existing silicon technology Vertical orientation  Cell area ↓ Placing defined numbers of nanotubes at selected locations

24. Summary : Remaining Obstacles High voltage  Vertical gate (14V  4V : still high) The growth temperature used in this work : 600–650 o C is relatively high for integration with CMOS technology Still larger (~200nm ) : Need demonstration at smaller size is needed Randomization of nanotube orientation by thermal fluctuations and gas flows

25. References “ Nanoscale memory cell based on a nanoelectromechanical switched capacitor”, J. E. Jang, et al. (Samsung Advanced Institute of Technology & U of Cambridge) Nature 26 Nanotechnology | VOL 3 | JANUARY 2008 “Nanoelectromechanical switch with low voltage drive” J. E. Jang, et al. APPLIED PHYSICS LETTERS 93, 113105 2008 Internet search – DRAM / CNT etc.

26. Thank you very much See you again! Q&A