Presentation is loading. Please wait.

Presentation is loading. Please wait.

Design Considerations in CLBs for Deep Sub-Micron Technologies Louis Alarcón Octavian Florescu.

Published by Modified over 9 years ago

Similar presentations

Presentation on theme: "Design Considerations in CLBs for Deep Sub-Micron Technologies Louis Alarcón Octavian Florescu."— Presentation transcript:

1 Design Considerations in CLBs for Deep Sub-Micron Technologies Louis Alarcón Octavian Florescu

2 Motivation As technology scales… –The effects due to process variations will become more pronounced. Regular structures are needed to mitigate these effects. –Leakage will increase as the V TH are scaled. Low leakage architectures will be needed to control stand-by power.

3 Configurable Logic Block Stack –Regular –Low Leakage –Slow due to RC delay Current Sensing –Recover performance loss through smaller voltage swings. Data Inputs S S OUT CLK Program Bits Pass Transistor Stack Pass Transistor Stack Current Sense Current Sense

4 Root Input A B S S P0P0 Programming (P 0, P 1, P 2, P 3 ) Logic to sense amp A B B B The Stack Inverted multiplexer tree “pseudo-differential” currents at the outputs Data inputs: 4 Program bits: 16

5 I ON I OFF  0 V1V1 V2V2 I BIAS I1I1  V = V 1 - V 2 > 0 V1V1 V2V2 I ON I OFF CLB V1V1 V2V2 I ON I OFF DCVSL-based Sense Amplifier (DCVSL-SA) Clamped Bit-Line Sense Amplifier (CBL) Conditional Precharge Sense Amplifier (CP) Sense Amplifier Topologies

6 I ON I OFF  0 V1V1 V2V2 I BIAS I1I1  V = V 1 - V 2 > 0 V1V1 V2V2 I ON I OFF CLB V1V1 V2V2 I ON I OFF DCVSL-based Sense Amplifier (DCVSL-SA) Clamped Bit-Line Sense Amplifier (CBL) Conditional Precharge Sense Amplifier (CP) Sense Amplifier Topologies

7 I ON I OFF  0 V1V1 V2V2 I BIAS I1I1  V = V 1 - V 2 > 0 V1V1 V2V2 I ON I OFF CLB V1V1 V2V2 I ON I OFF DCVSL-based Sense Amplifier (DCVSL-SA) Clamped Bit-Line Sense Amplifier (CBL) Conditional Precharge Sense Amplifier (CP) Sense Amplifier Topologies

8 I ON I OFF  0 V1V1 V2V2 I BIAS I1I1  V = V 1 - V 2 > 0 V1V1 V2V2 I ON I OFF CLB V1V1 V2V2 I ON I OFF DCVSL-based Sense Amplifier (DCVSL-SA) Clamped Bit-Line Sense Amplifier (CBL) Conditional Precharge Sense Amplifier (CP) Sense Amplifier Topologies

9 EDP and Leakage CMOS TG CBL CP DCVSL-SA Looks too good to be true? It probably is… EDP CMOS TG CBL CP DCVSL-SA Leakage Current

10 CLB (Stack) CLB (Stack) CP SA CP SA I ON I OFF  V SA Root Input I ON  V SA Process Variation and Mismatch  V should be > 0 for proper sensing I ON,min needed by the sense amplifier upsize

11 Sizing for Yield CBL CP DCVSL-SA CBL CP DCVSL-SA EDP Leakage Current Yield Target: 99% (Monte Carlo process and mismatch simulations) needs to be verified in silicon

12 Constant Yield Lines Solid line has a 99% yield over all process corners. –Overkill? The yield increases as V DD increases CP (Upsized) CLB: 10x CP Sense Amp: 2x CP EDP CP Performance Loss

13 Constant Yield Lines Dash-dotted line represents a constant Yield Line. Size of CLB tailored to desired Yield and V DD. 99% yield line A B CP (Upsized) CLB: 10x CP Sense Amp: 2x CP Yield B = Yield A EDP CP

14 Constant Yield Lines 99% yield line CP (Upsized) CLB: 10x CP Sense Amp: 2x CP EDP CP CMOS TG CP Upsized EDP Yield B = Yield A A B

15 Constant Yield Lines CBL 99% line A B CBL (Upsized) CBL Yield B = Yield A EDP CBL CMOS TG CBL CP Upsized EDP

16 Constant Yield Lines DCVSL-SA 99% line A B DCVSL-SA (Upsized) DCVSL-SA Yield B = Yield A EDP CMOS TG CBL CP DCVSL-SA Upsized EDP

17 EDP and Yield CMOS TG CBL CP DCVSL-SA EDP (w/o sizing for yield) CMOS TG CBL CP DCVSL-SA EDP (constant yield)

18 EDP and Yield CMOS TG CBL CP DCVSL-SA EDP (w/o sizing for yield) CMOS TG CBL CP DCVSL-SA EDP (constant yield) High Voltage Space

19 DCVSL-SA best performing SA, and competitive with current TG and CMOS implementations. However… More difficult to design –Analog-like design process Less versatile –Mandatory latch at the output –DVS Higher design risk –6  unacceptable Summary of Results CMOS TG CBL CP DCVSL-SA EDP (constant yield) CMOS TG CBL CP DCVSL-SA Leakage Current

20 Summary of Results DCVSL-SA best performing SA, and competitive with current TG and CMOS implementations. However… More difficult to design –Analog-like design process Less versatile –Mandatory latch at the output –DVS Higher design risk –6  unacceptable

21 Sense Amplifiers in Future Technologies Design of Sense Amplifiers in the future will become more challenging. –Impact of process variations will become more pronounced –V DD will continue to scale  V SA /V DD increases  V TH /V DD increases The useful design space will be limited. –Low leakage environments –High voltage, low energy space

22 Thank you

23 Design Considerations in CLBs for Deep Sub-Micron Technologies Louis Alarcon Octavian Florescu

24 Energy – Delay CMOS TG CBL CP DCVSL-SA CBL CP DCVSL-SA

25 Low Threshold Voltage CMOS TG CBL CP DCVSL-SA

Download ppt "Design Considerations in CLBs for Deep Sub-Micron Technologies Louis Alarcón Octavian Florescu."

Similar presentations

Digital to Analog Converter By Rushabh Mehta Manthan Sheth.

Digital to Analog Converter By Rushabh Mehta Manthan Sheth.
Semiconductor Memory Design. Organization of Memory Systems Driven only from outside Data flow in and out A cell is accessed for reading by selecting.

Semiconductor Memory Design. Organization of Memory Systems Driven only from outside Data flow in and out A cell is accessed for reading by selecting.
Robust Low Power VLSI R obust L ow P ower VLSI Sub-threshold Sense Amplifier (SA) Compensation Using Auto-zeroing Circuitry 01/21/2014 Peter Beshay Department.

Robust Low Power VLSI R obust L ow P ower VLSI Sub-threshold Sense Amplifier (SA) Compensation Using Auto-zeroing Circuitry 01/21/2014 Peter Beshay Department.
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM.

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM.
Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS INVERTER.

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS INVERTER.
Reducing Read Latency of Phase Change Memory via Early Read and Turbo Read Feb 9 th 2015 HPCA-21 San Francisco, USA Prashant Nair - Georgia Tech Chiachen.

Reducing Read Latency of Phase Change Memory via Early Read and Turbo Read Feb 9 th 2015 HPCA-21 San Francisco, USA Prashant Nair - Georgia Tech Chiachen.
Introduction to CMOS VLSI Design Lecture 13: SRAM

Introduction to CMOS VLSI Design Lecture 13: SRAM
A 16-Bit Kogge Stone PS-CMOS adder with Signal Completion Seng-Oon Toh, Daniel Huang, Jan Rabaey May 9, 2005 EE241 Final Project.

A 16-Bit Kogge Stone PS-CMOS adder with Signal Completion Seng-Oon Toh, Daniel Huang, Jan Rabaey May 9, 2005 EE241 Final Project.
Fall 06, Sep 19, 21 ELEC5270-001/6270-001 Lecture 6 1 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic.

Fall 06, Sep 19, 21 ELEC / Lecture 6 1 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic.
Designing Combinational Logic Circuits: Part2 Alternative Logic Forms:

Designing Combinational Logic Circuits: Part2 Alternative Logic Forms:
11/29/2004EE 42 fall 2004 lecture 371 Lecture #37: Memory Last lecture: –Transmission line equations –Reflections and termination –High frequency measurements.

11/29/2004EE 42 fall 2004 lecture 371 Lecture #37: Memory Last lecture: –Transmission line equations –Reflections and termination –High frequency measurements.
1 A Variation-tolerant Sub- threshold Design Approach Nikhil Jayakumar Sunil P. Khatri. Texas A&M University, College Station, TX.

1 A Variation-tolerant Sub- threshold Design Approach Nikhil Jayakumar Sunil P. Khatri. Texas A&M University, College Station, TX.
Week 7a, Slide 1EECS42, Spring 2005Prof. White Week 7a Announcements You should now purchase the reader EECS 42: Introduction to Electronics for Computer.

Week 7a, Slide 1EECS42, Spring 2005Prof. White Week 7a Announcements You should now purchase the reader EECS 42: Introduction to Electronics for Computer.
Introduction to CMOS VLSI Design SRAM/DRAM

Introduction to CMOS VLSI Design SRAM/DRAM
Device Sizing Techniques for High Yield Minimum-Energy Subthreshold Circuits Dan Holcomb and Mervin John University of California, Berkeley EE241 Spring.

Device Sizing Techniques for High Yield Minimum-Energy Subthreshold Circuits Dan Holcomb and Mervin John University of California, Berkeley EE241 Spring.
Die-Hard SRAM Design Using Per-Column Timing Tracking

Die-Hard SRAM Design Using Per-Column Timing Tracking
Low-Power CMOS SRAM By: Tony Lugo Nhan Tran Adviser: Dr. David Parent.

Low-Power CMOS SRAM By: Tony Lugo Nhan Tran Adviser: Dr. David Parent.
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 31: Array Subsystems (SRAM) Prof. Sherief Reda Division of Engineering,

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 31: Array Subsystems (SRAM) Prof. Sherief Reda Division of Engineering,
Design and Implementation of VLSI Systems (EN0160) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley.

Design and Implementation of VLSI Systems (EN0160) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley.
Towards An Efficient Low Frequency Energy Recovery Dynamic Logic Sujay Phadke Advanced Computer Architecture Lab Department of Electrical Engineering and.

Towards An Efficient Low Frequency Energy Recovery Dynamic Logic Sujay Phadke Advanced Computer Architecture Lab Department of Electrical Engineering and.

Similar presentations

Ads by Google