1. Basic Computer Organization CH-4 Richard Gomez 6/14/01 Computer Science Quote: John Von Neumann If people do not believe that mathematics is simple, it is only because they do not realize how complicated life is.

2. 3 Fundamental Components of Computer n The CPU (ALU, Control Unit, Registers) n The Memory Subsystem (Stored Data) n The I/O subsystem(I/O devices) I/O Device Subsystem Address Bus Data Bus Control Bus CPU Memory Subsystem

3. Each of these Components are connected through Buses. n BUS - Physically a set of wires. The components of the Computer are connected to these buses. n Address Bus n Data Bus n Control Bus

4. Address Bus n Used to specify the address of the memory location to access. n Each I/O devices has a unique address. (monitor, mouse, cd-rom) n CPU reads data or instructions from other locations by specifying the address of its location. n CPU always outputs to the address bus and never reads from it.

5. Data Bus n Actual data is transferred via the data bus. n When the cpu sends an address to memory, the memory will send data via the data bus in return to the cpu.

6. Control Bus n Collection of individual control signals. n Whether the cpu will read or write data. n CPU is accessing memory or an I/O device n Memory or I/O is ready to transfer data

7. I/O Bus or Local Bus n In today’s computers the the I/O controller will have an extra bus called the I/O bus. n The I/O bus will be used to access all other I/O devices connected to the system. n Example: PCI bus

8. Instruction Cycles n Procedure the CPU goes through to process an instruction. n 1. Fetch - get instruction n 2. Decode - interperate the instruction n 3. Execute - run the instruction.

9. Process of an Instruction (Define fetch) n When CPU is ready the it will assert the read control signal. n Depending on the CPU the read can be active high (1) or low (0). n After being asserted the subsystem will return the data through the data bus. n The CPU will then receive this data and store into one of its registers

10. Process of an Instruction (Define Decode) n Now the CPU will decode the instruction. n The CPU will determine the sequences of commands needed to perform. n Each instruction can require different sequences of operations. n This is perform within the CPU with no system buses.

11. Process of an Instruction (Define Execute) n The CPU will now execute the instruction. n This sequence will vary from different instructions. n Read or write data to memory or I/O subsystem.

12. Timing Diagram: Memory Read n Address is placed at beginning of clock n after one clock cycle the CPU asserts the read. n Causes the memory to place its data onto the data bus. n CLK : System Clock used to synchronize CLK Address Bus Read Data

13. Timing Diagram : Memory Write n CPU places the Address and data on the first clock cycle. n At the start of the second clock the CPU will assert the write control signal. n This will then start memory to store data. n After some time the write is then deasserted by the CPU after removing the address and data from the subsystem. CLK Address Address Bus Data Bus Read Data

14. I/O read and Write Cycles n The I/O read and Write cycles are similar to the memory read and write. n Memory mapped I/O : Same sequences as input output to read and write. n The processor treats an I/O port as a memory location. n This results in the same treatment as a memory access.

15. CPU organization n CPU controls the Computer n The CPU will fetch, decode and execute instructions. n The CPU has three internal sections: register section, ALU and Control Unit

16. Register Section n Includes collection of registers and a bus. n Processor’s instruction set architecture are found in this section. n Non accessible registers by the programmer. These are to be used for registers to latch the address being accessed and a temp storage register.

17. Arithmetic/Logic Unit (ALU) n Performs most Arithmetic and logical operations. n Retrieves and stores its information with the register section of the CPU.

18. Memory Subsystem n 2 Types of Memory: –ROM : Read Only Memory n Program that is loaded into memory and cannot be changed also retains its data even without power. –RAM : Random Access Memory n Also called read/write memory. This type of memory can have a program loaded and then reloaded. It also loses its data with no power.

19. Different ROM Chips n Masked ROM : n ROM that is programmed with data when fabricated. Data will not change once installed. Hardwired. n Programmable ROM (PROM) : n Capable of being programmed by the user with a ROM programmer. Not hardwired. n Erasable PROM (EPROM) : n Much like the PROM this EPROM can be programmed and then erased by light. n EEPROM : n Another form of EPROM but is reprogammable electrically.

20. Different RAM Chips n Dynamic RAM (DRAM) : n Leaky capacitors. Caps are charged and slowly leak until they are refreshed to there original data locations. Ex. Computer RAM n Static RAM (SRAM) : n Much like a register. The contents stay valid and does not have to be refreshed. SRAM is faster than DRAM but cost more Ex. Cache –Each RAM chip has 2^n * m. n address inputs and m bidirectional data pins

21. Internal Memory Organization n ROM and RAM have similar internal organization. n Internal linear Organization. Ex. 8 X 2 ROM Chip: A2 A1 A0 Decoder 0123456701234567 3-8 E CE OED0 0 D1 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

22. Internal Memory Cont. n This chip has 3 Address inputs n 2 data outputs n 16 bits of internal storage arranged as 8 2-bit locations n The 3 address bits will be decoded to select one of the 8 locations only if CE is active (1). n With both CE and OE enabled the buffers are enabled and data is allowed to flow out.

23. Internal Memory Cont. n As the # of locations increases the size of the address decoder needed in linear organization becomes very large. n To get around this problem we can use multi-dimensions of decoding. n The size of an n to 2^n decoder is said to be O(2^n)

24. Memory Subsystem n Memory subsystem is the combination of memory chips n Example : 8 x 2 chips can be combined to make an 8 x 4 memory. n Both chips will receive the same 3 address inputs from the bus, as well as the CE and OE signals. n The data pins of the first chip are connected to bits 3 and 2 and the other to 1 an 0 of the data bus

25. Memory Subsystem Cont. n When the CPU reads data it places the address on the address bus. n Both chips will read in bits A1, A2, and A0 and decode n Since both chips are using the same CE and OE either both chips are active or not. n To the CPU it will act just like an 8 x 4 memory chip.

26. Von Neumann and Harvard architectures n Are similar in implementation using this diagram. n They differ in how data is arranged in memory. n The Neumann uses mixed memory module while the Harvard uses separate memory modules for data and instructions I/O Device Subsystem Address Bus Data Bus Control Bus CPU Memory Subsystem

27. Von Neumann and Harvard architectures n Modern computers today predominantly use the Neumann architecture. n Although it will also use some elements of the harvard architecture. n The difference is the PC will assign sections of memory to either instructions or data. n Although this is not a true Harvard architecture because that system requires that a memory module always be assign the same one of the two.