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S. Reda EN1600 SP’08 Design and Implementation of VLSI Systems (EN0160) Lecture 28: Datapath Subsystems 4/4 Prof. Sherief Reda Division of Engineering,

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Presentation on theme: "S. Reda EN1600 SP’08 Design and Implementation of VLSI Systems (EN0160) Lecture 28: Datapath Subsystems 4/4 Prof. Sherief Reda Division of Engineering,"— Presentation transcript:

1 S. Reda EN1600 SP’08 Design and Implementation of VLSI Systems (EN0160) Lecture 28: Datapath Subsystems 4/4 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2 S. Reda EN1600 SP’08 D. Shifters Shifting a data word by a constant amount is trivial A programmable shifter is more complex Multibit shifter can be cascaded together

3 S. Reda EN1600 SP’08 Barrel Shifter Signal passes through at most one transmission gate Total transistors = N 2 Dominated by wiring

4 S. Reda EN1600 SP’08 Logarithmic shifter Total shift is decomposed into stages of 2 Speed of shifting N bits depends on log N Number of transistor = 2(log N)* N

5 S. Reda EN1600 SP’08 E. Multipliers

6 S. Reda EN1600 SP’08 Array multiplier Where is the critical path?

7 S. Reda EN1600 SP’08 Critical path of MxN multiplier

8 S. Reda EN1600 SP’08 Carry Save Multiplier The carry bits are not immediately added, but rather are “saved” for the next adder stage The vector merge adder should be a fast carry lookahead adder T mult = t and +(N-1)t carry +t merge

9 S. Reda EN1600 SP’08 Summary A.Adders B.0/1 detectors C.Comparators D.Shifters E.Multipliers


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