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1 Lab7 Design and Implementation
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2 Design Example
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3 Computer to D2E Board Print Port
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4 Boards Interconnection~~ D2E Connect to DIO1 Port A Port B
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5 Power to D2E Board 變壓 整流器 AC 110V DC 5V
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6 Create a New Project
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7 Enter a Name and Location for the Project 1 2 3 4 檔名開頭請勿使用數字或特殊符號並不要使用中文為檔名
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8 Select Device Family, Package, Device and Speed Grade 1 2
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9 Create a New Source
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10 Next Step
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11 Finish
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12 Create a New File 1 3 2
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13 You can type Verilog on the New File
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14 You can type Verilog on the New File 1 2
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15 Type “ logic.v ” Module name and File name must the same. 1 2
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16 Add Source 1.Right Click 2
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17 Select “ logic.v ” 1 2 3
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18 Add Test Bench Waveform 1.Right Click 2 3 4 5 檔名開頭請勿使用數字或特殊符號 並不要使用中文為檔名
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Check Synthesize Double Click
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Select Source File 20 1 2
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New Source Information 21
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22 Select Design Type 1 2
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Waveform Created by HDL Bencher 23
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Select Behavioral Simulation 24 1 2
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25 Give Input Value 1 2.Save
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26 Generate Expected Simulation Result Double Click 2
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27 Result F=(x & ~y) | (y | z)
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28 Add Implementation Constraints File 1.Right Click 2 3 4 5 檔名開頭請勿使用數字或特殊符號 並不要使用中文為檔名
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New Source Information 29
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Select Synthesis/Implementation 30 2 1
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31 Assign Package Pins 2. Double Click 1
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32 Assign Pins [1] DIO1 D2E Signal Sw1 P16 x Sw2 P18 y Sw3 P21 z LD1 P44 F ※請注意看板子,子板跟母板連接是使用哪一個 Port ※ Port A DIO1 D2E Signal Sw1 P126 x Sw2 P129 y Sw3 P133 z LD1 P154 F Port C
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33 Assign pins [2]
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34 Assign pins [3] 1 2. Save 3 4
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35 Run “ Implement Design ” 1 2. Double Click
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36 View/Edit Routed Design Double Click
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37 View Routed Design
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38 Select FPGA Start-Up Clock to JTAG Clock 1. Right Click 2 3 4 3 4 5
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39 Generate Bitstream File Double Click
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40 Run “ Configure Device ” Double Click 此時請務必將版子接上
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41 Select Boundary.. and Automatically … 2 1
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42 Select “ logic.bit file ” 2 1 3
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43 Right-click to select operation 2 1.Right Click
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44 Click “ ok ”
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45 Check the Results on Emulation Board
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46 Question and Answer 歷史人物中,誰跑最快 ?
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