1. 1 Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4) Presentation 9 MAD MAC 525 29 th March, 2006 Functional Block Simulations W2 Project Objective: Design a crucial part of a GPU called the Multiply Accumulate Unit (MAC) which will revolutionize graphics. Design Manager: Zack Menegakis

2. 2 MAD MAC 525 Status: Project chosen Specifications defined Architecture Design Behavioral Verilog Testbenches Verilog : Gate Level Design Floor plan Schematics and Analog Verifications Layout of basic gates and small modules Spring Break Top level layouts, extractions, LVS, simulations (in progress) To be done  Full chip layout and simulation

3. 3 RegArray ARegArray BRegArray C Multiplier Exp CalcAlign Adder/Subtractor Control Logic & Sign Dtrmin Normalize Round Ovf Checker Leading 0 Anticipator 10 5 5 5 14 35 22 5 4 36 14 10 1 5 5 Input Output 16 Reg Y 15 1 1 1 Block Diagram

4. 4 Design Decisions Removed carry select top adder bits –Reduced hardware at the cost of speed –Speed still well within required parameters –Easier to layout

5. 5 Pipelining Stages Multiplier Align C Reg A Reg B Exp Calc Reg C Pipeline Reg Adder Ld Zero Pipeline Reg Normalize Round Reg Y Pipeline Reg Overflow checker Pipeline Reg

6. 6 Timing Diagram Pipeline stage 1 Pipeline stage 2 Pipeline stage 3 Pipeline stage 4 Pipeline stage 5 Multiplier lower 7 outputs Multiplier mid 4 outputs Multiplier top 11 outputs AdderNormalize Exponent calculator AlignInvert Adder inputs Zero Counter Round Holds exponent calculator Overflow Checker

7. 7 New Floorplan

8. 8 Newer Floorplan

9. 9 Adder Schematic

10. 10 Adder Bit Slice Layout

11. 11 Adder Layout

12. 12 Adder Schematic Simulation

13. 13 Adder Layout Simulation

14. 14 Adder Schematic vs Layout Layout is 19% slower than schematic –Layout = 1150ps –Schematic = 962ps Other logic in adder module will slow it down further –Expecting about 1.6-1.8ns total –Well within 2ns target

15. 15 Transisto r Count Area in um 2 Prop. Delay Power in mW (350MHz) Multiplier3600165604.64n8.5 Exponents738 3800942p1.608 Align500 2990637p0.393 Adder3174158701.7n5.236 Leading 0364 1222551p0.857 Normalize942520434p2.291 Round462 2310948p0.631 OvfCheck100 500475p0.13 Registers1850 9200120p- Total 1173055628--

16. 16 Normalize Layout

17. 17 Normalize Layout Simulation

18. 18 Problems Cadence refused to extractRC some of our modules –Turns out that Cadence discriminates against certain output pins for a reason we cannot yet determine –Solution was to copy output pins from modules that work when running extractRC and rename them Certain group members not happy with group picture –Solution is to take a new picture, iron out the wrinkles & photoshop our project manager in

19. 19 Questions??