1. Kabuki 2800 “a real-time digital audio effects system for performance” team “Big Country” presents ECEN4610 Preliminary Design Review 14 September 2006

2. Agenda 1. Project overview 2. Architecture 3. Implementation 4. Risk management 5. Division of labor 6. Schedule

3. OVERVIEW Design goal Customizeable and extensible real- time digital audio effects system for live performance

4. Project overview Target consumer Live performance! Electronic composers Electronic musicians Mic’ed acoustic musicians

5. Project overview Current status Kabuki 1200 Summer ‘06 Some effects Slider input No custom effects Slow display

6. Project overview Kabuki 2800 baseline requirements Computer control+display interface Support for saved presets Custom effects Time-domain base effects Portable

7. Project overview Kabuki 2800 secondary requirements Interchangeable human input board FFT coprocessor for performance Frequency-domain effects

8. Block Diagram Kabuki 2800 Summer Progress

9. IMPLEMENTATION How is it all going to work? 1. Effects 2. I/O Card 3. Touchscreen 4. Performance Module 5. DSP Co-Processing X XX X XX XXX S F H

10. Effects (on DSK) Filter and Equalizer FIR IIR Echo & Reverb Buffering Flange Fancy Buffering Granulation Crazy Buffering Pitch Time Shifting -FFT and/or wavelet transform Etc..

11. I/O Card EMIF Computer Interrupts

12. I/O Card FPGAAltera Cyclone I/II 3-8ns propogation low-cost FIFO “MegaFunction” Clock Source: buffered clock from EMIF

13. USB: DLP Designs USB to parallel module (USB Control Cores for FPGAs) RS-232 MAX3232 1Mbit/s 2Tx & 2Rx EMIF bus: (drive and voltage change) MAX3000E Converts voltage levels from 1.2 5.5 Volts Mostly PCB and some Wire-Wrap I/O Card

14. Performance Module FPGA to handle communication and device polling. 4-5 foot buttons (Directly into logic device) 1-2 Pedals Pedals act as attenuators Feed 5V signal AD7861 (ADC with 11bit resolution) Low speed PLCC 44 package Clock Source: Crystal Oscillator (1MHz)

15. DSP Co-processor TMS3206713B-200 200pin HLQFP Not BGA!!! Connection through Host Peripheral Interface on DSK 192K internal SRAM Maybe enough! Clock Source: same as DSK, 50MHz Crystal Oscillator. HPI

16. Touch Screen Motion Computing M1300 Slate style tablet: large screen Linux Preset Programming Slider Display

17. Development Structure Primary Secondary Kabuki 2800

18. Dan’s Tasks Primary Software Effects Software Devices Software simulation Secondary Layout design and fabrication. Firmware Kabuki 2800

19. Justin’s Tasks Primary I/O Layout Design and Fabrication Firmware USB design and Protocols Secondary Does No have any. Kabuki 2800

20. Tim’s Tasks Primary Performance board firmware layout and design Kabuki 2800 Secondary USB Design and Protocols Device Casing

21. Yazan Task’s Primary Device Casing and Fabrication DSK and interface Card Kabuki 2800 Secondary Module hardware design Module Firmware design Audio effect algorithm simulation Audio effect algorithm Final packaging and Software

22. Phase 1 – Milestone 1, Nov. 2 Phase 2 – Milestone 2, Nov. 30 Phase 3 – Expo, Dec. 14 Schedule

23. Phases Phase 1 – Development & Prototyping Phase 2 – Integration Phase 3 – Testing and Production

24. FPGA configured FPGA boots from EEPROM FLASH reads/writes properly DSK I/O Firmware Complete USB tested RS-232 interface tested Performance Board Performance Board Phase 1

25. FPGA configured and tested Performance Board Performance Board Phase 2

26. All interfaces fully functional (RS-232, USB) Flash storage able to load / store presets I/O functions with DSK and DSP co- processor USB firmware interfaces with FPGA and with host computer RS-232 interface fully functioning Firmware completed and under testing Communication established with DSP coprocessor. I/O Board I/O Board Phase 3

27. FPGA configured and tested FPGA boots from EEPROM A/D converter tested Firmware in testing Performance Board Performance Board Phase 1

28. FPGA interfaces with I/O board Foot – pedals generate interrupts A/D converter samples fader pedal Performance Board Performance Board Phase 2

29. FPGA interfaces with Interface Card All user inputs are fully functional Performance Board Performance Board Phase 3

30. Board Layout Complete DSP Coprocessor DSP Coprocessor Phase 1

31. Board fabricated, populated and ready for testing JTAG ready DSP Coprocessor DSP Coprocessor Phase 2

32. DSP Processor is able to implement FFT and Wavelet Transforms DSP is able to communicate with I/O board and and co-process transforms DSP Coprocessor DSP Coprocessor Phase 3

33. Effect Algorithms Effect Algorithms Phase 1 Time Domain Effects Simulated Phasing Filters Etc.

34. Most time domain effects simulated Several more time domain effects implemented FFTs simulated in Matlab Effect Algorithms Effect Algorithms Phase 2

35. Time Domain effects implemented FFT and Wavelet Domain effects simulated and implemented Effect Algorithms Effect Algorithms Phase 3

36. RISKS AND CONTINGENCY PLAN Sources of Risk USB interface RS-232 interface DSP co-processor Touch-screen interface

37. USB FIFO Interface RISKS: Needs Windows DLLs to be recognized Must interface with FPGA Timing CONTINGENCY PLAN USE RS-232 USE Preprogrammed Flash Memory

38. RS-232 Interface RISKS Communication is not fast enough Timing CONTINGENCY PLAN Make the performance board stackable on top of the existing DSK

39. DSP co-processor RISKS: Timing Memory Interface CONTINGENCY PLAN: Eliminate effects that need extensive FFT / wavelet processing Use the existing DSK to implement transforms

40. Touch-screen Interface RISKS: USB must work We must be able to access the Windows dll files to monitor touches We must be able to monitor touches on the screen in real-time CONTINGENCY PLAN: Use sliders / faders