1. Viterbi Decoder: Presentation #3 Omar Ahmad Prateek Goenka Saim Qidwai Lingyan Sun M1 Overall Project Objective: Design of a high speed Viterbi Decoder Stage 3: 2 Feb. 2004 Size Estimates/ Floorplan Design Manager: Yaping Zhan

2. Status Design Proposal (finalized) Architecture Proposal (done) Behavioral -> Structural Verilog (done) Floor-planning and size estimates (done) To be done: Schematics of Design (20% done) Component Layout Chip Layout Spice Simulation of Entire Chip 18-525, Integrated Circuits Design Project

3. Design Decisions: Metal Directionality M1 M2 M3 M4 Metal usage: Vdd! – M1, M2 Gnd! – M1, M2 Internal Routing – M1, M2 Clock – M3, M4 Reset – M3, M4 Global Routing – M3, M4

4. 18-525, Integrated Circuits Design Project Design Decisions: Adders Ripple-carryCarry look-aheadVs. 5 gates/bit ~34 transistors/bit For 8 bits ~ 40 gates Easy to implement Slightly faster Harder logic Too big ~ 35 gates/4 bits ~14,000 transistors for all adders in design Decision? Ripple-carry chosen & used Mirror Adders ~28 transistors/bit

5. a7a6a5a4a3a2a1a0 a7a6a5a4a3a2a1a0 a0a7a0a6a0a5a0a4a0a3a0a2a0a1a0a0 a1a6a1a5a1a4a1a3a1a2a1a1a0a1 A2a5a2a4a2a3a2a2a1a2a0a2 a3a4a3a3a2a3a1a3a0a3 a3a4a2a4a1a4a0a4 a2a5a1a5a0a5 a1a6a0a6 a7a6a5a4a3a2a1a0 a7a6a5a4a3a2a1a0 Xa0a5a0a4a0a3a0a2a0a10a0 Xa1a4a1a3a1a2a1 Xa2a3a2 Xa3 Design Decisions: Simpler Multiplier 18-525, Integrated Circuits Design Project Chosen

6. Design Decisions: Trace back unit Place each flip-flop & mux pair like this? Or like this? Too long Chosen 18-525, Integrated Circuits Design Project

7. Design Decisions: Dealing with Clock skew 18-525, Integrated Circuits Design Project Possible ideas:  Tapering  Buffering  H-Tree Clock

8. 18-525, Integrated Circuits Design Project Floor Plan: Top Level Sizing ML Search 250 140 ACS Unit 650 70 BCU Unit 650 40 TB Unit 170 70 All units in microns

9. 18-525, Integrated Circuits Design Project Floor Plan: Top Level Routing ML Search ACS Unit BCU Unit TB Unit clk rst 650 350 All units in microns Buffering/Routing

10. Floor Plan: Branch Calculation Unit 18-525, Integrated Circuits Design Project FlipFlops …………………….. 650 40 All units in microns

11. Floor Plan: Add Compare Select Unit 18-525, Integrated Circuits Design Project Flip Flop ……………………. Flip Flop Adder ……………………. Subtractor Mux Flip Flop ……………………. Flip Flop ……………………. 70 650 All units in microns

12. Floor Plan: ML Search 18-525, Integrated Circuits Design Project 8 Bit Subtractor 8 Bit Mux + Flop 8 Bit Subtractor 3 Bit Mux + Flop 3 Bit Mux + Flop 3 Bit Mux + Flop 3 Bit Mux + Flop 3 Bit Mux + Flop 3 Bit Mux + Flop 8 Bit Subtractor 8 Bit Mux + Flop 3 Bit Mux + Flop 250 140 All units in microns

13. Floor Plan: Trace Back Unit 18-525, Integrated Circuits Design Project Mux Dff …… Dff …………………………………………………. …… 170 70 All units in microns

14. New Transistor Counts Trace Back Unit: D-Flip Flops 8 x 17 x 12 = 1,632 2:1 Multiplexers 8 x 16 x 14 = 1,792 Total 3,424 Branch Calculation Unit: D-Flip Flops 4 x 17 x 12 + 8 x 16 x 12 = 2,352 Adders 4 x 16 x 28 = 1,792 8 bit Multipliers 16 x 150 = 2,400 Total 6,544 Add Compare Select Unit: D-Flip Flops 8 x 24 x 12 + 1 x 8 x 12 = 2,400 2:1 Multiplexers 8 x 8 x 14 = 896 Adders 8 x 16 x 28 = 3,584 Subtracters 8 x 8 x 29 = 1,856 Total 8,736 Maximum Likelihood Search Unit: D-Flip Flops 8 x 6 x 12 + 3 x 7 x 12 = 828 2:1 Multiplexers 8 x 6 x 14 + 3 x 7 x 14 = 966 Comparators 8 x 7 x 32 = 1,792 Adders 4 x 1 x 28 = 112 Total 3,698 Grand Total = 22,402! Key: No. of bits x No. of elements x No. of transistors/bit

15. Transistor Counts Previous Vs. Revised 18-525, Integrated Circuits Design Project Adders 2:1 Multiplexers Multipliers Registers Total 9,136 3,654 2,400 7,212 22,402 5,900 1,056 3,840 2,400 14,196 PreviousRevised

16. 18-525, Integrated Circuits Design Project Structural Verilog

17. 18-525, Integrated Circuits Design Project Structural Verilog Simulation

18. Questions? 18-525, Integrated Circuits Design Project