1. S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 18: Static Combinational Circuit Design (2/2) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2. S. Reda EN160 SP’07 Last lecture Conversion of AND/OR circuits to NAND/NOR/INV circuits. An asymmetric gate favor one input over the other(s). A skewed gate favor one transition over the other(s).

3. S. Reda EN160 SP’07 What is the P/N ratio that gives the least delay? We have selected P/N ratio for unit rise and fall resistance (  = 2-3 for an inverter). Alternative: choose ratio for least average delay By sacrificing rise delay, pMOS transistors can be downsized to reduced input capacitance, average delay, and total area

4. S. Reda EN160 SP’07 pMOS is the enemy! –High input and diffusion capacitance for a given current Can we take the pMOS capacitance off the input? Various circuit families try to do this…

5. S. Reda EN160 SP’07 Let’s get rid of pMOS Reduced the capacitance and improved the delay  Increased static power consumption How can we implement the R easily in a CMOS process? [see subsection 2.5.4]

6. S. Reda EN160 SP’07 1. Pseudo-nMOS circuits In the old days, nMOS processes had no pMOS –Instead, use pull-up transistor that is always ON In CMOS, use a pMOS that is always ON –Ratio issue –Make pMOS about ¼ effective strength of pulldown network [see subsection 2.5.4]

7. S. Reda EN160 SP’07 Logical effort of pseudo-nMOS gates Design for unit current on output to compare with unit inverter. pMOS fights nMOS logical effort independent of number of inputs!

8. S. Reda EN160 SP’07 Pseudo-nMOS power Pseudo-nMOS draws power whenever Y = 0 –Called static power P = IV DD –A few mA / gate * 1M gates would be a problem –This is why nMOS went extinct! Use pseudo-nMOS sparingly for wide NORs Turn off pMOS when not in use

9. S. Reda EN160 SP’07 Ganged CMOS When A=B=0: both pMOS turn on in parallel pulling the output high fast When both inputs are ‘1’: both pMOS transistors turn off saving power over psuedo-nMOS When one is ‘1’ or one is ‘0’ then it is just like the pseudo-nMOS case Traditional pseudo-nMOS

10. S. Reda EN160 SP’07 2. Cascode Voltage Switch Logic (CVSL) Seeks the performance of pseudo-nMOS without the static power consumption CVSL disadvantages: –Require input complement –NAND gate structures can be tall and slow

11. S. Reda EN160 SP’07 3. Pass Transistor Logic Problem: ‘1’ is not passed perfectly cannot the output to the input of another gate Advantage: just uses two transistors

12. S. Reda EN160 SP’07 Complementary Pass Transistor Logic (CPTL) Complementary data inputs and outputs are available Very suitable for XOR realization (compare to traditional CMOS) Interconnect overhead to route the signal and its complement A B A B B BBB A B A B F=AB F=AB F=A+B F=A+B BB A A A A F=A  F=A OR/NOR EXOR/NEXOR AND/NAND F F Pass-Transistor Network Pass-Transistor Network A A B B A A B B Inverse (a) (b)

13. S. Reda EN160 SP’07 Possible solution: interface to a CMOS inverter Threshold voltage loss causes static power consumption M 2 M 1 M n M r Out A B V DD V Level Restorer X A better design: full swing; reduces static power (AKA Lean Integration with Pass Transistors - LEAP)

14. S. Reda EN160 SP’07 Pass Transistor Logic with transmission gates In pass-transistor circuits, inputs are also applied to the source/drain terminals. Circuits are built using transmission gates. Problem: Non-restoring logic. Traditional CMOS “rejuvenates” signals

15. S. Reda EN160 SP’07 Restoring Pass Transistor Logic Next time: Dynamic circuits