1. Final Presentation Momentum Measurement Card Project supervised by: Mony Orbach Project performed by: Hadas Preminger, Uri Niv

2. Final Presentation Introduction Developing an electronic card capable of measuring momentum. Implementation: FPGA (Field Programmable Gate-Array) USB to FIFO module. C++ application.

3. Final Presentation Input Signals Two 2bits signals: Each signal consists of two square waves, with 90° phase difference. Currently these signals are generated by the FPGA. Usb connection to PC.

4. Final Presentation Output Signals A file, consists of two dimension array [position1_, position2_ ]. The length of the array: 600 measurements (for each cart). The position of the cart at the beginning of the experiment is set to be “0”. +/- represents the position in reference to the zero point.

5. Final Presentation System Rates Hardware Rates: Main clock rate 12MHz Logical Unit to DLP data transfer 32 bits/sample Send/Receive data over USB up to 1Mbits/sec Sampling & Processing rates: Number of samples per cart 600 samples Sample resolution8 counts/mm Time between samples (Tick length)10ms or 5ms Cart minimum/maximum speed0-5 meter/sec

6. Final Presentation The Experiment ’ s System The experiment consists of : Two carts on an air track moving towards each other. On each cart there is a "Miller Strip“. Two positioning sensors.

7. Final Presentation The Exp. Sensor Output We get better resolution 1 mm Count Signal A Signal B A xor B Counts

8. Final Presentation Block Diagram Logical Unit USB Communication Unit Data Position Measuring System 2 Optical Encoders Control Software

9. Final Presentation Electrical Structure FPGA Transceivers 3.3V5V DLPDLP CLK Flat Cable Logical Unit Board USB comm. Board EPC2Reset

10. Final Presentation Electrical Structure – Logical Unit The FPGA and EPC2: The FPGA is a FLEX 10k100ARC by ALTERA which has 240 pins. The original ALTERA has 189 I/O pins. We currently use 51 of them. The FPGA's configuration is done through the EPC2 configuration device. 3 TI Transceivers.

11. Final Presentation Electrical Structure – USB Board Consists of DLP Design USB245m – a USB transmit/receive adapter, with a T/R FIFO buffer. In the second part, the sensors will be connected to this board.

12. Final Presentation The Logical Unit : A 12MHz frequency oscillator. Two power supply units: 3.3 Volts (FPGA and EPC2). 5 Volts (TI transceivers). The DLP uses bus power of 5volts (from PC). Electrical Structure – Power and Clock

13. Final Presentation FPGA Inner Structure General: The Logical Unit has two main tasks: Sample and calculate the position of the cart. Control the transmission process to the PC. Those two tasks are done by two separate blocks. These two blocks are synchronized by specially designated signals.

14. Final Presentation FPGA Inner Structure- Top Level Data_ Genera tor Input’s Async To Sync Signal1 Signal2 Calc_ Coord Operating _ Machine Start Control Signals Carts’ coordination Control’s Async To Sync Control Signals from DLP DLP Control Signals 8bit Data Bus Control signal Data signal

15. Final Presentation Top Level structure Consist of 5 main blocks: A block that samples & calculates the coordination of the carts. A control block that is synchronized with the PC and controls the transmission process to the PC. This control unit actually controls the DLP module. Two Async to Sync units. A data generator.

16. Final Presentation Data_Generator The data_generator replaces the EM1 sensor's input signal during the first phase of the project.

17. Final Presentation Async to Sync Blocks Convert the asynchronous input signals to synchronous signals by sampling the input signal using two D-Flip-Flops.

18. Final Presentation Calc_Coord Block Samples the input signal and calculates the position of the carts. Creates the signal ‘Counts’. Determines the direction of the cart. Counts the number of ‘counts’ from the beginning. BA 00 10 11 01 R L

19. Final Presentation Operating_Machine Block The core of the whole system. It is synchronized with the PC application. Controls the USB comm. module. Implemented by a Finite State Machine. The OM block’s main tasks are: Receiving the sampling interval from the PC. Sampling the counter of the Calc_Coord block at every interval. Sending the data to the PC via the USB module.

20. Final Presentation Operating_Machine Block

21. Final Presentation Read Byte Cycle

22. Final Presentation Operating_Machine Block

23. Final Presentation Write Byte Cycle

24. Final Presentation Application & Drivers A Visual C++ application was written to: Establish a real time connection between the peripheral hardware and the PC. Supply a basic user’s interface. We referred to the USB protocol as a “Black Box”. The communication between the hardware and the software is done automatically by the operating system of the PC.

25. Final Presentation Application & Drivers DLP Design supplies two kinds of interfaces for the application software developer. The solution of an Interface that uses a DLL was chosen.

26. Final Presentation Application & Drivers The driver’s architecture for the DLL interface are: Application Software Visual C++ Ftd2xx.dll Ftd2xx.sys Operating System – Windows USB Driver Stack USB245M The application software is compiled with a.lib file, which connects the application during run-time, to the.dll file. Windows USB Interface – via USB stack. Application Software Interface

27. Final Presentation Application & Drivers CommentsFile descriptionFile Name The file is one of the files included in the DLL package of drivers. This heeder file must be included to the project in order to use the DLP system calls. Ftd2xx.h 1. In this header file, the declarations of the utility functions, which are used by main.cpp, are made. Function.h 2.2. In this header file, the declarations of the main classes of the program are made. Momentum.h 3.3. Implementation. Function.cpp 4.4. Implementation. Momentum.cpp 5. Implementation of the "main" program. Main.cpp 6.6.

28. Final Presentation Application ’ s Flow Chart Initialize USB connection Is a device connected? No Ask user for time between samples Yes

29. Final Presentation Application ’ s Flow Chart Send time between samples to hardware Take a sample 600 samples? No Yes End

30. Final Presentation Application ’ s Classes Based on two important classes: Position and DLP. The DLP class manages the communication between the application and the USB. The Position class manages and stores the information that is received from the hardware.

31. Final Presentation Summary We have learned a lot. Main problems we dealt with: Communication. Different ways of debug. For the next part: Design a PCB. Reduce costs. Improve reliability.