1. CMS Electronics Week November 2002 1 Electronics Issues Drew Baden University of Maryland USCMS HCAL

2. CMS Electronics Week November 2002 2 InstallationInstallation

3. 3 VME Racks

4. CMS Electronics Week November 2002 4

5. 5 HCAL Clocking

6. CMS Electronics Week November 2002 6 Clocking Changes TTC Fanout Board TTCrx TTC 80 MHz Clock PECL HTR Board TTCrx SLB Board (holds 6 SLBs) 80 MHz LVPECL Crystal 1 to 8 Fanout 1  2 Fanout Single width VME BC0 L1A 40MHz TTCrx TTC TTC Broadcast Cat 5 quad cable 80 MHz LVPECL Crystal 1 to 8 Fanout Double width VME BC0 80MHz 40MHz TI (16) FPGAFPGA Clock/2 SLB TI (16) FPGAFPGA TTC BC0 L1A 40MHz BC0 40MHz L1A BC0 40MHz PECL 1 to 8 Fanout 40 MHz system 80MHz PECL TTC mezz TTC LVDS/ PECL Depends on which input used…. TTC broadcast bus 40 MHz clean 80 MHz system Cat 6/7 quad cable (allows LVDS/PECL) TTC Fanout Board OLD SCHEMATIC NEW SCHEMATIC QPLL

7. CMS Electronics Week November 2002 7 New clock Scheme TTCrx QPLL TTC BC0 CC40 CC80 ‘CC’ means Clean Clock Cat6/7 RJ45 RJ45 TTCMezz TTC SLB CC40 BC0 Xilinx CC80 TTC broadcast, L1A, BCR, EVR, CLK40

8. CMS Electronics Week November 2002 8 Fanout – HTR scheme HTR TTC fiber TTC LVDS CLK80 3.3V-PECL RX_BC0 LVDS Cat6E or Cat7 cable 8 clks to TLKs DS90LV001 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 MC100LVE310 3.3V PECL CLK40 3.3V-PECL LVDS Fanout x 8 PCK953 LVPECL- to-LVTTL Fanout (top layer) PCK953 LVPECL- to-LVTTL Fanout (top layer) 8 clks to TLKs + TPs To 6 SLBs Diff. to 2 Xilinx + termin. Diff. to 6 SLBs Single-end to 2 xilinx TTC daughter card IN IN_b Brdcst, BrcstStr, L1A, BCntRes to xilinx and SLBs CLK80 LVDS Fanout Board Low-jitter Fanout x 15 O/E Brdcst, BrcstStr BC0 Fanout buffer TTC FPGA Fanout x 15 Brdcst, BrcstStr, BCntRes, L1A CMOS LVDS or diff PECL …….. 15 connectors on bottom layer ? 15 Cables & Connectors tbd …….. NB100LVEP221 is LVDS compatible TTCrx (or daughter card) QPLL AN1568/D Fig 11 Onsemi.com RJ45 ~Fifteen RJ45 connectors PECL fanout e.g. DS90LV110.. 2 Test Points for CLK40 and BC0 CLK40 LVDS PECL fanout.. 80.0789 MHz 3.3V crystal Diff. PECL MC100LVEL37 CK CK/2.. 9U Front-panel space = 325 mm ; => space per connector ~ 21.5 mm Notes: SLBs require fanout of CLK40, BC0. FE-link possibly requires CLK80. PECL fanout was tested in TB2002. One Cat6E cable (low x-talk) replaces the 2 Cat5 cables used in TB2002. TTC and BC0 remain LVDS as in Weiming’s board. HTR needs Broadcast bus, BCntRes and L1A: from TTCrx if we get it to work, otherwise we have to fan them out. LVDS Tullio Grassi

9. CMS Electronics Week November 2002 9 HCAL TriDAS Integration First integration completed, summer 02 FE  HTR  DCC  SLINK  CPU All links well established No obvious clocking problems Work needed on synch monitoring and reporting Improvements expected using crystal for TI refclk Will always have TTC/QPLL clock as backup… HTR firmware fairly mature Switch to Virtex2 all but complete TPG and BCID ready but not tested To commence when next HTR version delivered and Wisconsin TPG boards delivered (est Q4 2002) Will be main effort when next HTR version arrives Dec 2002

10. CMS Electronics Week November 2002 10 Integration Goals 2003 Continued development of HTR and DCC firmware Commission TPG path Firmware, LUTs, synchronization, SLB output… Monitoring, error reporting, etc. (both cards) We need to settle on where the preliminary US-based integration will take place We propose that this be at FNAL Full system as in the previous testbeam Except TPG which will be done initially at UMD Moved to FNAL if needed Testbeam in the summer (to begin in spring) Same goals as summer 02 – support calibration effort and continue commissioning the system Operate a “vertical slice” for an extended period of time, Fall 03 Fully pipelined, monitoring, TPG, DAQ, synchronization, clocking…. Develop software to support DAQ activities Testbeam software improvements Software for commissioning HTR needed Allow us to verify fiber mapping Download LUTs, firmware version, etc.

11. CMS Electronics Week November 2002 11 Overall Commissioning Schedule Summer 2003 testbeam Repeat previous test w/production prototype boards Fall 2003 Slice tests HCAL will join as schedule allows 2003/2004 HCAL burn-in Continue with firmware development/integration as needed 2004/2005 Vertical Slice and magnet test We will be ready All HCAL TriDas production cards involved October 05 beneficial occupancy of USC Installation of all racks, crates, and cards We do not anticipate any hardware integration Should be all firmware / timing / troubleshooting

12. CMS Electronics Week November 2002 12 ScheduleSchedule

13. CMS Electronics Week November 2002 13 Installation Requirements Production cards will be available, all systems Front-end emulator will be critical No other way to light up the fibers during installation Design very close to actual front-end card (GOL, not TI) Built by FNAL Close interaction with UMD on board UMD firmware HCAL mapping nightmare will have to be implemented very carefully Will need to be able to connect to rack CPU from inside shield wall as we plug the fibers in one at a time Will need to have audio communication between operators inside shield wall and at VME racks

14. CMS Electronics Week November 2002 14 Installation Manpower Needs Drawing on D  Level 2 experience for the current Tevatron Run 2a… Each significant card requires on-site expertise: Probably 1-2 postdoc-level (or above) and 1 engineer Maybe the same engineer for both DCC and HTR… HCAL will have an electronics setup at CERN Total personnel estimate: Front End 1 HTR 2 DCC 2 Miscellaneous (grad students, transients, etc.) maybe 4? Very difficult to say with any accuracy