1. Spring 07, Feb 15 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Power Dissipation in VLSI Chips Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07

2. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)2 ISSCC, Feb. 2001, Keynote “Ten years from now, microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second – about the same number of calculations that the world's fastest supercomputer can perform now. “Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor....” Patrick P. Gelsinger Senior Vice President General Manager Digital Enterprise Group INTEL CORP.

3. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)3 VLSI Chip Power Density 4004 8008 8080 8085 8086 286 386 486 Pentium® P6 1 10 100 1000 10000 19701980199020002010 Year Power Density (W/cm 2 ) Hot Plate Nuclear Reactor Rocket Nozzle Sun’s Surface Source: Intel 

4. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)4 SIA Roadmap for Processors (1999) Year199920022005200820112014 Feature size (nm) 180130100705035 Logic transistors/cm 2 6.2M18M39M84M180M390M Clock (GHz) 1.252.13.56.010.016.9 Chip size (mm 2 ) 340430520620750900 Power supply (V) 1.81.51.20.90.60.5 High-perf. Power (W) 90130160170175183 Source: http://www.semichips.orghttp://www.semichips.org

5. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)5 Recent Data Source: http://www.eetimes.com/story/OEG20040123S0041

6. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)6 Low-Power Design  Design practices that reduce power consumption at least by one order of magnitude; in practice 50% reduction is often acceptable.  Low-power design methods:  Algorithms and architectures  High-level and software techniques  Gate and circuit-level methods  Test power  ELEC 6270: Low-Power Design of Electronic Circuits, generally offered in the fall semester; course discusses power dissipation mechanism in CMOS devices, power optimization methods, power analysis, and system level power optimization.

7. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)7 VLSI Building Blocks  Finite-state machine (FMS)  Bus  Flip-flops and shift registers  Memories  Datapath  Processors

8. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)8 State Encoding for a Counter  Two-bit binary counter:  State sequence, 00 → 01 → 10 → 11 → 00  Six bit transitions in four clock cycles  6/4 = 1.5 transitions per clock  Two-bit Gray-code counter  State sequence, 00 → 01 → 11 → 10 → 00  Four bit transitions in four clock cycles  4/4 = 1.0 transition per clock  Gray-code counter is more power efficient. G. K. Yeap, Practical Low Power Digital VLSI Design, Boston: Kluwer Academic Publishers (now Springer), 1998.

9. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)9 Binary Counter: Original Encoding Present state Next state abAB 0001 0110 1011 1100 A = a’b + ab’ B = a’b’ + ab’ ABAB a b CK CLR

10. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)10 Binary Counter: Gray Encoding Present state Next state abAB 0001 0111 1000 1110 A = a’b + ab B = a’b’ + a’b ABAB a b CK CLR

11. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)11 Three-Bit Counters BinaryGray-code State No. of toggles State 000-000- 00110011 01020111 01110101 10031101 10111111 11021011 11111001 00030001 Av. Transitions/clock = 1.75 Av. Transitions/clock = 1

12. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)12 N-Bit Counter: Toggles in Counting Cycle  Binary counter: T(binary) = 2(2 N – 1)  Gray-code counter: T(gray) = 2 N  T(gray)/T(binary) = 2 N-1 /(2 N – 1) → 0.5 BitsT(binary)T(gray)T(gray)/T(binary) 1221.0 2640.6667 31480.5714 430160.5333 562320.5161 6126640.5079 ∞--0.5000

13. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)13 FSM State Encoding 11 0100 0.1 0.4 0.3 0.6 0.9 0.6 01 1100 0.1 0.4 0.3 0.6 0.9 0.6 Expected number of state-bit transitions: 1(0.3+0.4+0.1) + 2(0.1) = 1.0 Transition probability based on PI statistics State encoding can be selected using a power-based cost function. 2(0.3+0.4) + 1(0.1+0.1) = 1.6

14. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)14 FSM: Clock-Gating  Moore machine: Outputs depend only on the state variables.  If a state has a self-loop in the state transition graph (STG), then clock can be stopped whenever a self- loop is to be executed. Sj Si Sk Xi/Zk Xk/Zk Xj/Zk Clock can be stopped when (Xk, Sk) combination occurs.

15. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)15 Clock-Gating in Moore FSM Combinational logic Latch Clock activation logic Flip-flops PI CK PO L. Benini and G. De Micheli, Dynamic Power Management, Boston: Springer, 1998.

16. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)16 Bus Encoding for Reduced Power  Example: Four bit bus  0000 → 1110 has three transitions.  If bits of second pattern are inverted, then 0000 → 0001 will have only one transition.  Bit-inversion encoding for N-bit bus: Number of bit transitions 0 N/2N N N/2 0 Number of bit transitions after inversion encoding

17. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)17 Bus-Inversion Encoding Logic Polarity decision logic Sent data Received data Bus register Polarity bit M. Stan and W. Burleson, “Bus-Invert Coding for Low Power I/O,” IEEE Trans. VLSI Systems, vol. 3, no. 1, pp. 49-58, March 1995.

18. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)18 Clock-Gating in Low-Power Flip-Flop D Q D CK

19. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)19 Reduced-Power Shift Register D Q D CK(f/2) multiplexer Output Flip-flops are operated at full voltage and half the clock frequency.

20. Spring 07, Feb 15ELEC 7770: Advanced VLSI Design (Agrawal)20 Power Consumption of Shift Register P = C’V DD 2 f/n Degree of parallelism, n 1 2 4 Normalized power 1.0 0.5 0.25 0.0 Deg. Of parallelism Freq (MHz) Power (μW) 133.01535 216.5887 48.25738 16-bit shift register, 2μ CMOS C. Piguet, “Circuit and Logic Level Design,” pages 103-133 in W. Nebel and J. Mermet (ed.), Low Power Design in Deep Submicron Electronics, Springer, 1997.