1. EECC722 - Shaaban #1 lec # 9 Fall 2006 10-23-2006 Computing System Element Choices Specialization, Development cost/time Performance/Chip Area/Watt (Computational Efficiency) Programmability / Flexibility General Purpose Processors Application Specific Processors Re-configurable Hardware ASICs Superscalar VLIW DSPs Network Processors Graphics Processors ….. Reconfigurable Computing Also known as Custom Computing Machines (CCMs) Utilize hardware devices customized to match computation Using: FPGAs (Fine grain) or Micro-coded arrays of simple processors (coarse grain) GPPs Co-Processors

2. EECC722 - Shaaban #2 lec # 9 Fall 2006 10-23-2006 Spatial vs. Temporal Computing SpatialTemporal Processor Instructions (using hardware) (using software/program) Defined by fixed functionality and connectivity of hardware elements Processor running Processor running programs written using a pre-defined fixed set of instructions (ISA)

3. EECC722 - Shaaban #3 lec # 9 Fall 2006 10-23-2006 Computing Element Programmability Defining Terms Computes one function (e.g. FP-multiply, divider, DCT) Function defined at fabrication time e.g ASICs Computes “any” computable function (e.g. Processor, DSPs, FPGAs) Function defined after fabrication Fixed Function:Programmable: Parameterizable Hardware: Performs limited “set” of functions e.g. Co-Processors

4. EECC722 - Shaaban #4 lec # 9 Fall 2006 10-23-2006 Computing Element Choices Observation Generality and efficiency are in some sense inversely related to one another: –The more general-purpose a computing element is and thus the greater the number of tasks it can perform, the less efficient it will be in performing any of those specific tasks. –Design decisions are therefore almost always compromises; designers identify key features or requirements of applications that must be met and and make compromises on other less important features. To counter the problem of computationally intense problems for which general purpose machines cannot achieve the necessary performance: –Special-purpose processors, attached processors, and coprocessors have been built for many years, especially in such areas as image or signal processing (for which many of the computational tasks can be very well defined). –The problem with such machines is that they are special-purpose; as problems change or new ideas and techniques develop, their lack of flexibility makes them problematic as long-term solutions. Reconfigurable computing or Custom Computing Machines (CCMs) using econfigurableReconfigurable computing or Custom Computing Machines (CCMs) using FPGAs (Field Programmable Gate Arrays, first introduced in 1986 by Xilinx) or other reconfigurable (customizable) hardware can offer an attractive alternative to other computing element choices. FPGAs originally developed for hardware design verification, rapid-prototyping, and potential ASIC-replacement Due to fixed ISA

5. EECC722 - Shaaban #5 lec # 9 Fall 2006 10-23-2006 What is Reconfigurable Computing? Utilize Utilize reconfigurable hardware devices: (spatially-programmed connections of hardware processing elements) tailored to application: Customizing hardware to match computations needed/present in a particular application by changing hardware functionality on the fly. Reconfigurable Computing Goal Reconfigurable Computing Goal: Using reconfigurable hardware devices to build systems with advantages over conventional computing solutions in terms of: - Flexibility - Performance - Power - Time-to-market - Life cycle cost “Hardware” customized to specifics of problem. Direct map of problem specific dataflow, control. Circuits “adapted” as problem requirements change. Computational Efficiency Hardware customization/reconfigurablity, how? Change both function of hardware cells (elements) and their connectivity to match requirements of Computation/application Still spatial computing but both functionality and connectivity of hardware elements are not fixed

6. EECC722 - Shaaban #6 lec # 9 Fall 2006 10-23-2006 Conventional Programmable Processors Vs. Configurable devices Conventional Programmable Processors: Moderately wide datapath which have been growing larger over time (e.g. 16, 32, 64, 128 bits). Support for large on-chip instruction caches which have also been been growing larger over time that can now hold thousands of instructions. High bandwidth instruction distribution so that several instructions may be issued per cycle at the cost of dedicating considerable die area for instruction fetch/distribution/issue/scheduling. A single thread of computation control per processor core. (SMT changes this) Configurable devices (such as FPGAs): Narrow datapath (e.g. almost always one bit), CLB)On-chip space for only one instruction per compute element -- i.e. the single instruction which tells the FPGA array cell (Configurable Logic Block, CLB) what function to perform and how to route its inputs and outputs (connectivity to other cells). Minimal die area dedicated to instruction distribution such that it takes hundreds of thousands of compute cycles to change the active set of array instructions (e.g From one FPGA configuration to another). Can handle regular and bit-level computations more efficiently than processors.

7. EECC722 - Shaaban #7 lec # 9 Fall 2006 10-23-2006 Why Reconfigurable Computing? To improve performance (including predictability) and computational energy efficiency over a software implementation. – e.g. signal processing applications in configurable hardware. Provide powerful, application-specific operations. To improve product flexibility and development cost/time compared to hardware (ASIC) – e.g. encryption, compression or network protocols handling in configurable hardware To use the same hardware for different purposes at different points in the computation (lowers cost). –Given sufficient use of each configuration to tolerate potentially long reconfiguration latency/overheads

8. EECC722 - Shaaban #8 lec # 9 Fall 2006 10-23-2006 Benefits of Reconfigurable Logic Devices Non-permanent customization and application development after fabrication –“Late Binding” Economies of scale (amortize large, fixed design costs) Shorter time-to-market than ASICs (dealing with evolving requirements and standards, new ideas) Potential Disadvantages: Efficiency penalty (area, performance, power) compared to ASICs. Need for correctness Verification. (common to all hardware-based solutions) Customization achieved by changing both function of hardware elements and their connectivity to match requirements of application

9. EECC722 - Shaaban #9 lec # 9 Fall 2006 10-23-2006 Spatial/Configurable Hardware Benefits/Drawbacks Potentially, an order of magnitude (10x) or higher raw computational density advantage over processors. Potential for fine-grained (bit-level) control/parallelism --- can offer another order of magnitude benefit. Locality. Each compute/interconnect resource dedicated to single function. Must dedicate resources for every computational subtask. Infrequently needed portions of a computation sit idle --> inefficient use of resources Spatial/Configurable Drawbacks (but much better than processors)

10. EECC722 - Shaaban #10 lec # 9 Fall 2006 10-23-2006 Configurable Computing Application Areas Digital signal processing Encryption Image processing Telemetry Data processing (remote-sensing) Data/Image/Video compression/decompression Low-power (through hardware "sharing") Scientific/Engineering physical system modeling (e.g. finite-element computations). Network applications (e.g. reconfigurable routers) Variable precision arithmetic Logic-intensive applications In-the-field hardware enhancements Adaptive (learning) hardware elements Rapid system prototyping Verification of processor and ASIC designs …... In general many types of applications with few computationally intensive “kernels” (inner-loops?) that can done more efficiently in hardware Original applications of FPGAs

11. EECC722 - Shaaban #11 lec # 9 Fall 2006 10-23-2006 Technology Trends Driving Configurable Computing Increasing gap between "peak" performance of general-purpose processors and "average actually achieved" performance. –Most programmers don't write code that gets anywhere near the peak performance of current superscalar CPUs Improvements in FPGA hardware: capacity and speed: –FPGAs use standard SRAM processes and "ride the commodity technology" curve (e.g. VLSI technology) –Volume pricing even though customized solution Improvements in synthesis and FPGA mapping/routing software Increasing number of transistors on a (processor) chip (one billion+): How to use them efficiently? –Bigger caches (Most popular)? –Multiple processor cores? (Chip Multiprocessors - CMPs) –SMT support? –IRAM-style vector/memory? –DSP cores or other application specific processors? –Reconfigurable logic (FPGA or other reconfigurable logic)? A Combination of the above choices? Heterogeneous Computing System on a Chip?

12. EECC722 - Shaaban #12 lec # 9 Fall 2006 10-23-2006 Configurable Computing Configurable Computing Architectures Configurable ComputingConfigurable Computing architectures combine elements of general-purpose computing and application-specific integrated circuits (ASICs). –The general-purpose processor operates with fixed circuits that perform multiple tasks under the control of software. –An ASIC contains circuits specialized to a particular task and thus needs little or no software to instruct it. The configurable computer can execute software commands that alter its configurable devices (e.g FPGA circuits) as needed to perform a variety of jobs. i.e to change both functionality and connectivity of hardware elements (cells)

13. EECC722 - Shaaban #13 lec # 9 Fall 2006 10-23-2006 Levels of the Reconfigurable Computational Elements (according to grain size) ReconfigurableLogicReconfigurableDatapathsReconfigurableArithmeticReconfigurableControl Bit-Level Operations e.g. encoding Dedicated data paths e.g. Filters, AGU Arithmetic kernels e.g. Convolution Configurable Processors Real-Time Operating Systems (RTOS): Process management e.g FPGAs Finer Grain Coarser Grain

14. EECC722 - Shaaban #14 lec # 9 Fall 2006 10-23-2006 Hybrid-Architecture Computer Combines general-purpose processors (GPPs) and reconfigurable devices, commonly: –FPGA chips (Fine-grain reconfigurable hardware), or –Micro-coded arrays of simple processors (Coarse-grain reconfigurable hardware). A controller FPGA may load circuit configurations stored in memory onto the processor FPGA in response to the requests of the operating program. If the memory does not contain a requested circuit, the processor FPGA sends a request to the PC host, which then loads the configuration for the desired circuit. Common Hybrid Configurable Architecture Today: – One or more FPGAs on board connected to host via I/O bus (e.g PCI) Possible Future Hybrid Configurable Architecture: –Integrate a region of configurable hardware (FPGA or something else) onto processor chip itself as reconfigurable functional units or coprocessors –Integrate configurable hardware onto DRAM chip=> Flexible computing without memory bottleneck Current Hybrid-Architecture on a chip: Hybrid FPGAs: Integrate one or more hard-wired GPPs with an FPGA on the same chip Example: Xilinx Vertex-II Pro, Virtex-4 FX (FPGA with one or two PowerPC cores)

15. EECC722 - Shaaban #15 lec # 9 Fall 2006 10-23-2006 Hybrid-Reconfigurable Computer: Levels of Coupling Different levels of coupling in a hybrid reconfigurable system. Reconfigurable logic is shaded. Reconfigurable functional units (on chip) Reconfigurable coprocessor (on or off chip) Attached (e.g. via PCI) reconfigurable processing unit (Most common today) External standalone processing unit (e.g. Via network/IO interface) Future direction ISA SupportFunction Calls Loose Coupling Tight Coupling

16. EECC722 - Shaaban #16 lec # 9 Fall 2006 10-23-2006 Configurable Computing Application: Sample Configurable Computing Application: Prototype Video Communications System Uses a single FPGA to perform four functions that typically require separate chips. A memory chip stores the four circuit configurations and loads them sequentially into the FPGA. Initially, the FPGA's circuits are configured to acquire digitized video data. The chip is then rapidly reconfigured to transform the video information into a compressed form and reconfigured again to prepare it for transmission. Finally, the FPGA circuits are reconfigured to modulate and transmit the video information. At the receiver, the four configurations are applied in reverse order to demodulate the data, uncompress the image and then send it to a digital-to-analog converter so it can be displayed on a television screen.

17. EECC722 - Shaaban #17 lec # 9 Fall 2006 10-23-2006 Early Configurable (or Custom) Computing Successes DEC Programmable Active Memories, PAM (1992): –A universal hardware FPGA-based co-processor closely coupled to a standard host computer developed at DEC's Paris Research Laboratory –Fast RSA decryption implementation on a reconfigurable machine (10x faster than the fastest ASIC at the time) Splash2 (1993): –Attached Processor System using Xilinx FPGAs as processing elements developed at Center for Computing Sciences. –Performs DNA Sequence matching 300x Cray2 speed, and 200x a 16K Thinking Machines CM2 speed Many modern processors and ASICs are verified using FPGA emulation systems For many digital signal processing/filtering (e.g FIR, IIR) algorithms, single chip FPGAs outperform DSPs by 10- 100x. (More on Splash 2 in lecture handout)

18. EECC722 - Shaaban #18 lec # 9 Fall 2006 10-23-2006 Programmable Circuitry: FPGAs Field-Programmable Gate Array (FPGA) introduced by Xilinx (1986). Original target applications: hardware design verification, rapid-prototyping, and potential ASIC-replacement. Programmable circuits can be created or removed by sending signals to gates in the logic elements (configuration bit stream). A built-in grid of circuits arranged in columns and rows allows the designer to connect a logic element to other logic elements or to an external memory or microprocessor. The logic elements are grouped in Configurable Logic Blocks (CLBs) that perform basic binary operations such as AND, OR and NOT Firms, including Xilinx and Altera, have developed devices with the capability of 4,000,000 or more equivalent gates. Recently, in addition to “ general-purpose” or generic FPGAs, more specialized FPGA families targeting specific areas such as DSP applications have been developed with hard-wired functional units (e.g. MAC units). Fine-grain Reconfigurable Hardware Devices:

19. EECC722 - Shaaban #19 lec # 9 Fall 2006 10-23-2006 Field Programmable Gate Arrays (FPGAs) Chip contains many small building blocks that can be configured to implement different functions. –These building blocks are known as CLBs (Configurable Logic Blocks) FPGAs typically "programmed" by having them read in a stream of configuration information from off-chip –Typically in-circuit programmable (As opposed to EPLDs -Electrically Programmable Logic Devices- which are typically programmed by removing them from the circuit and using a PROM programmer) 25% of an FPGA's gates are application-usable –The rest control the configurability, interconnects, etc. As much as 10X clock rate degradation compared to fully custom hardware implementations (ASICs) Typically built using SRAM fabrication technology. Since FPGAs "act" like SRAM or logic, they lose their program when they lose power. Configuration bits need to be reloaded on power-up. Usually reloaded from a PROM, or downloaded from memory via an I/O bus. Fine-grain Reconfigurable Hardware Devices:

20. EECC722 - Shaaban #20 lec # 9 Fall 2006 10-23-2006 Look-Up Table (LUT) In Out 00 0 01 1 10 1 11 0 2-LUT Mem In1 In2 Out K-LUT -- K input lookup table Any function of K inputs by programming table 4-LUT 2-LUT Fine-grain Reconfigurable Hardware Devices: FPGAs

21. EECC722 - Shaaban #21 lec # 9 Fall 2006 10-23-2006 Conventional FPGA Tile K-LUT (typical k=4) w/ optional output Flip-Flop ~ 75% of FPGA area ~ 25% of FPGA area Or configurable Logic Block (CLB) 4-LUT Fine-grain Reconfigurable Hardware Devices: FPGAs

22. EECC722 - Shaaban #22 lec # 9 Fall 2006 10-23-2006 A Generic Island-style FPGA Routing Architecture 64 CLBs (8x8) One Tile Customization achieved by changing both function of hardware elements (CLBs here) and their connectivity to match requirements of application Fine-grain Reconfigurable Hardware Devices: FPGAs CLB

23. EECC722 - Shaaban #23 lec # 9 Fall 2006 10-23-2006 Xilinx XC4000 Interconnect Fine-grain Reconfigurable Hardware Devices: FPGAs Customization achieved by changing both function of hardware elements (CLBs here) and their connectivity to match requirements of application

24. EECC722 - Shaaban #24 lec # 9 Fall 2006 10-23-2006 Xilinx XC4000 (CLB) Xilinx XC4000 Configurable Logic Block (CLB) Cascaded 4 LUTs (2 4-LUTs -> 1 3-LUT) Fine-grain Reconfigurable Hardware Devices: FPGAs

25. EECC722 - Shaaban #25 lec # 9 Fall 2006 10-23-2006 FPGAs vs. RISC Processors Computational Density Comparison RISC Processors FPGAs 10X Fine-grain Reconfigurable Hardware Devices: FPGAs

26. EECC722 - Shaaban #26 lec # 9 Fall 2006 10-23-2006 Processor vs. FPGA Area FPGA Processor Fine-grain Reconfigurable Hardware Devices: FPGAs

27. EECC722 - Shaaban #27 lec # 9 Fall 2006 10-23-2006 Programming/Configuring FPGAs (1) Hardware Design Specification: A hardware design to realize the selected hardware-bound computationally-intensive portion of the application is specified using RTL/HDL/logic diagrams. Synthesis & Layout: Vendor supplied device-specific software tools are used to convert the hardware design to netlist format. –(2) Partition the design into logic blocks (CLBs) : LUT Mapping –Then find a good (3) placement for each block and (4) routing between them Then the serial configuration bitstream is generated (5) and fed down to the FPGAs themselves –The configuration bits are loaded into a "long shift register" on the FPGA. – The output lines from this shift register are control wires that control the behavior of all the CLBs on the chip. Result of Hardware-Software Partitioning (co-design)

28. EECC722 - Shaaban #28 lec # 9 Fall 2006 10-23-2006 Programming/Configuring FPGAs LUT Mapping PlacementRouting Bitstream Generation Tech. Indep. Optimization Config. Data RTL (1) Hardware Design (2) Partition the design CLBs design CLBs (3) Placement for each CLB each CLB ( 4) Routing between CLBs CLBs (5) configuration bitstream bitstream generation generation

29. EECC722 - Shaaban #29 lec # 9 Fall 2006 10-23-2006 Reconfigurable Processor Tools Flow (Hardware/Software Co-design Process Flow) Customer Application / IP (C code) ARC Object Code C Compiler RTL HDL Linker Executable C Model Simulator Configuration Bits Synthesis & Layout C Debugger Development Board Portion to be done in Reconfigurable hardware (e.g FPGA) Portion be done in software (1) Hardware Design Specification (2) Partitioning (3) Placement (4) Routing (5) configuration bitstream bitstream generation generation Hybrid System

30. EECC722 - Shaaban #30 lec # 9 Fall 2006 10-23-2006 (1) Hardware Design Specification Starting Point: (1) Hardware Design Specification RTL –t=A+B –Reg(t,C,clk); Logic –O i =A i  i  C i –C i+1 = A i B i  B i C i  A i C i Programming/Configuring FPGAs RTL/HDL/logic diagrams

31. EECC722 - Shaaban #31 lec # 9 Fall 2006 10-23-2006 Programming/Configuring FPGAs (2) Partition the design into logic blocks (CLBs) : LUT Mapping

32. EECC722 - Shaaban #32 lec # 9 Fall 2006 10-23-2006 (3) Placement of CLBs Maximize locality –minimize number of wires in each channel –minimize length of wires –(but, cannot put everything close) Often start by partitioning/clustering State-of-the-art finish via simulated annealing Programming/Configuring FPGAs

33. EECC722 - Shaaban #33 lec # 9 Fall 2006 10-23-2006 Programming/Configuring FPGAs (3) Placement of CLBs

34. EECC722 - Shaaban #34 lec # 9 Fall 2006 10-23-2006 (4) Routing Between CLBs Often done in two passes: –Global to determine channel. –Detailed to determine actual wires and switches. Difficulty is: –Limited available channels. –Switchbox connectivity restrictions. Programming/Configuring FPGAs

35. EECC722 - Shaaban #35 lec # 9 Fall 2006 10-23-2006 Programming/Configuring FPGAs (4) Routing Between CLBs

36. EECC722 - Shaaban #36 lec # 9 Fall 2006 10-23-2006 Overall Configurable Hardware Approach Select critical portions or phases of an application where hardware customizations will offer an advantage: e.g. computationally intensive portion “kernel(s)” of application. Map those application phases to FPGA hardware: – Hand hardware design/RTL/VHDL – VHDL => synthesis & layout If it doesn't fit in FPGA, re-select application phase (smaller) and try again. Perform timing analysis to determine rate at which configurable design can be clocked. Write interface software for communication between main processor (GPP) and configurable hardware: –Determine where input / output data communicated between software and configurable hardware will be stored –Write code to manage its transfer (like a procedure call interface in standard software) –Write code to invoke configurable hardware (e.g. memory-mapped I/O) Compile software (including interface code) Send configuration bits to the configurable hardware Run program. Hardware-Software Partitioning

37. EECC722 - Shaaban #37 lec # 9 Fall 2006 10-23-2006 Configurable Hardware Configurable Hardware Application Challenges This process turns applications programmers into: – Part-time hardware designers. Performance analysis problems => what should we put in hardware? Hardware-Software Co-design problem Choice and granularity of computational elements. Choice and granularity of interconnect network. Synthesis problems Testing/reliability problems.

38. EECC722 - Shaaban #38 lec # 9 Fall 2006 10-23-2006 Issues in Using FPGAs for Reconfigurable Computing Hardware-Software Partitioning (co-design) Run-time reconfiguration latency/overhead –Time to load configuration bitstream – may take seconds (improving) Reconfiguration latency hiding techniques. I/O bandwidth limitations: Need for tight coupling. Speed, power, cost, density (improving) High-level language support (improving) Performance, space estimators Design verification Partitioning and mapping across several FPGAs Partial reconfiguration Configuration caching. Supported in some recent high-end FPGAs e.g Hybrid-FPGAs

39. EECC722 - Shaaban #39 lec # 9 Fall 2006 10-23-2006 Reconfigurable Computing Example Reconfigurable Computing Research Efforts PRISM (Brown) PRISC (Harvard) RC-1 DPGA-coupled uP (MIT) GARP (RC-3), Pleiades, … (UCB) OneChip (Toronto) RC-2 RAW (MIT) RC-4 REMARC (Stanford) RC-5 CHIMAERA RC-6 (Northwestern) DEC PAM Splash 2 NAPA (NSC) E5 etc. (Triscend)

40. EECC722 - Shaaban #40 lec # 9 Fall 2006 10-23-2006 Hybrid-Architecture RC Compute Models 1. Unaffected by array logic: Interfacing –Triscend E5 2.Dedicated IO Processor. –NAPA 1000 3.Instruction Augmentation: (Tight Coupling) –Special Instructions / Coprocessor Ops - PRISM (Brown, 1991) - PRISC (Harvard, 1994) - Chimaera (Northwestern, 1997) - GARP (Berkeley, 1997) - Virtex-4 FX (Xilinx) –VLIW/microcoded arrays extension to processor REMARC (Stanford, 1998) - Raw (MIT, 1997) - - - REMARC (Stanford, 1998) - Raw (MIT, 1997) - - - MorphoSys (UC Irvine, 2000) - MATRIX (MIT, 1997) - MorphoSys (UC Irvine, 2000) - MATRIX (MIT, 1997) - RaPiD (Reconfigurable Pipelined Datapaths) (University of Washington, 1996) - RaPiD (Reconfigurable Pipelined Datapaths) (University of Washington, 1996) - PipeRench (Carnegie Mellon, 1999) - PipeRench (Carnegie Mellon, 1999) - DAPDNA-2 (IPFlex Inc., 2004?) ……… - DAPDNA-2 (IPFlex Inc., 2004?) ……… 4.Autonomous co/stream processor –OneChip (Toronto, 1998) UsuallyFPGA-based Usually arrays of Simple processors See DAPDNA Handout

41. EECC722 - Shaaban #41 lec # 9 Fall 2006 10-23-2006 Hybrid-Architecture RC Compute Models: Interfacing Logic used in place of –ASIC environment customization –External FPGA/PLD devices Example –bus protocols –peripherals –sensors, actuators Case for: – –Always have some system adaptation to do – –Modern chips have capacity to hold processor + glue logic – –reduce part count – –Glue logic vary – –valued added must now be accommodated on chip (formerly board level)

42. EECC722 - Shaaban #42 lec # 9 Fall 2006 10-23-2006 Example: Interface/Peripherals Triscend E5

43. EECC722 - Shaaban #43 lec # 9 Fall 2006 10-23-2006 Hybrid-Architecture RC Compute Models: IO Processor Array dedicated to servicing IO channel –sensor, lan, wan, peripheral Provides –flexible protocol handling –flexible stream computation compression, encrypt (in- place) Looks like IO peripheral to processor Case for: – –many protocols, services – –only need few at a time – –dedicate attention, offload processor

44. EECC722 - Shaaban #44 lec # 9 Fall 2006 10-23-2006 NAPA 1000 Block Diagram RPC Reconfigurable Pipeline Cntr ALP Adaptive Logic Processor System Port TBT ToggleBus TM Transceiver PMA Pipeline Memory Array CR32 CompactRISC TM 32 Bit Processor BIU Bus Interface Unit CR32 Peripheral Devices External Memory Interface SMA Scratchpad Memory Array CIO Configurable I/O Reconfigurable IO Processor Example: NAPA 1000

45. EECC722 - Shaaban #45 lec # 9 Fall 2006 10-23-2006 NAPA 1000 as IO Processor SYSTEM HOST NAPA1000 ROM & DRAM Application Specific Sensors, Actuators, or other circuits System Port CIO Memory Interface Reconfigurable IO Processor Example: NAPA 1000

46. EECC722 - Shaaban #46 lec # 9 Fall 2006 10-23-2006 Hybrid-Architecture RC Compute Models: Instruction Augmentation Observation: Instruction Bandwidth –Processor can only describe a small number of basic computations in a cycle I bits  2 I operations –This is a small fraction of the operations one could do even in terms of w  w  w Ops w2 2 (2w) operations –Processor could have to issue w2 (2 (2w) -I) operations (instructions) just to describe some computations –An a priori selected base set of functions (via ISA instructions) could be very bad for some applications Motivation for application-specific processors/ISAs I = opcode size W = operand word size ASPs i.e Fixed ISA i.e per instruction

47. EECC722 - Shaaban #47 lec # 9 Fall 2006 10-23-2006 Instruction Augmentation Idea: –Provide a way to augment the processor’s instruction set (Base ISA) with operations needed by a particular application. –Close semantic gap / avoid mismatch between fixed ISA and application computational operations needed. What’s required: –Some way to fit augmented instructions into stream –Execution engine for augmented instructions: If programmable, has own instructions FPGA or array of simple micro-coded processors –Interconnect to augmented instructions. Hybrid-Architecture RC Compute Models:

48. EECC722 - Shaaban #48 lec # 9 Fall 2006 10-23-2006 First Effort In Instruction Augmentation: PRISM (Brown, 1991) Processor Reconfiguration through Instruction Set Metamorphosis (PRISM) FPGA on bus (similar to Splash 2) Access as memory mapped peripheral Explicit context management PRISM-1 –68010 (10MHz) + XC3090 –can reconfigure FPGA in one second –50-75 clocks for operations Instruction Augmentation

49. EECC722 - Shaaban #49 lec # 9 Fall 2006 10-23-2006 PRISM-1 Results Raw kernel speedups (IO configuration time not included?)

50. EECC722 - Shaaban #50 lec # 9 Fall 2006 10-23-2006 PRISC (Harvard, 1994) Takes next step –What if we put it on chip? –How to integrate into processor ISA? Architecture: –Couple into register file as “superscalar” functional unit –Flow-through array (no state) Instruction Augmentation (paper RC-1) PRISC = PRogrammable Instruction Set Computers PFU = Programmable Functional Unit Tight Coupling

51. EECC722 - Shaaban #51 lec # 9 Fall 2006 10-23-2006 PRISC ISA Integration –Add expfu instruction (execute programmable functional unit) to MIPS ISA –11 bit address space for user defined expfu instructions –Fault on pfu instruction mismatch trap code to service instruction miss –All operations occur in one clock cycle –Easily works with processor context switch No state in PFU+ fault on mismatch pfu instruction Requested Logical PFU Function Number (paper RC-1) PFU = Programmable Functional Unit i.e combinational logic PFU

52. EECC722 - Shaaban #52 lec # 9 Fall 2006 10-23-2006 PRISC Results All compiled working from MIPS binary <200 4LUTs ? –64x3 200MHz MIPS base SPEC92 (paper RC-1)

53. EECC722 - Shaaban #53 lec # 9 Fall 2006 10-23-2006 Chimaera (Northwestern, 1997) Start from PRISC idea –Integrate as functional unit –No state –RFUOPs (like expfu): Reconfigurable FU Operation –Stall processor on instruction miss, reload Adds: –Manage multiple instructions loaded –More than 2 inputs possible Instruction Augmentation (paper RC-6) i.e > 2 operand registers

54. EECC722 - Shaaban #54 lec # 9 Fall 2006 10-23-2006 Chimaera Architecture “Live” copy of register file values feed into array Each row of array may compute from register values or intermediates (other rows) Tag on array to indicate RFUOP (paper RC-6) Major difference from PRISC: More than two register inputs possible FPGA-Like Array

55. EECC722 - Shaaban #55 lec # 9 Fall 2006 10-23-2006 Chimaera Architecture Array can compute on values as soon as placed in register file Logic is combinational When RFUOP matches –stall until result ready critical path –only from late inputs –Drive result from matching row (paper RC-6) No state in array

56. EECC722 - Shaaban #56 lec # 9 Fall 2006 10-23-2006 GARP (Berkeley, 1997) Integrates configurable array (FPGA) as coprocessor –Similar bandwidth to processor as FU –Own access to memory Support multi-cycle operation –Allow state –Cycle counter to track operation Fast operation selection –Cache for multiple configurations –Dense encodings, wide path to memory Instruction Augmentation (paper RC-3)

57. EECC722 - Shaaban #57 lec # 9 Fall 2006 10-23-2006 GARP Augmented MIPS ISA -- coprocessor operations –Issue gaconfig to make a particular configuration resident ( may be active or cached ) –Explicitly move data to/from array 2 writes, 1 read (like FU, but not 2W+1R) –Processor suspend during co-processor operation Cycle count tracks operation –Array may directly access memory Processor and array share memory space –cache/mmu keeps consistent between Can exploit streaming data operations (paper RC-3)

58. EECC722 - Shaaban #58 lec # 9 Fall 2006 10-23-2006 GARP Processor Instructions Augmented to MIPS ISA (paper RC-3) Get results from array Pass operands to array Load a configuration

59. EECC722 - Shaaban #59 lec # 9 Fall 2006 10-23-2006 GARP Array Row oriented logic –Denser for datapath operations Dedicated path for –Processor/memory data Processor does not have to be involved in array  memory path. (paper RC-3) FPGA-Like Array

60. EECC722 - Shaaban #60 lec # 9 Fall 2006 10-23-2006 GARP Results General results –10-20x on stream, feed- forward operation –2-3x when data- dependencies limit pipelining (paper RC-3) FPGA-Like Array

61. EECC722 - Shaaban #61 lec # 9 Fall 2006 10-23-2006 PRISC/Chimera vs. GARP PRISC/Chimaera –Basic op is single cycle: expfu ( rfuop ) –No state –Could conceivably have multiple PFUs? –Discover parallelism => run in parallel? –Can’t run deep pipelines –Configurable array has no direct access to memory GARP – –Basic op is multicycle gaconfig mtga mfga – –Can have state/deep pipelining – – Multiple arrays viable? – –Identify mtga/mfga w/ corr gaconfig ? – –Configurable array has access to memory

62. EECC722 - Shaaban #62 lec # 9 Fall 2006 10-23-2006 Common Instruction Augmentation Features To get around instruction expression limits: –Define new instruction in array (FPGA usually) Many bits of config … broad expressability Many parallel operators –Give array configuration short “name” which processor can callout (augmented instructions) …effectively the address of the operation

63. EECC722 - Shaaban #63 lec # 9 Fall 2006 10-23-2006 Hybrid-Architecture RC Compute Models: VLIW/microcoded Model Similar to instruction augmentation Usually utilize micro-coded arrays of simple processors (Coarse-grain reconfigurable hardware, not FPGAs). Single tag (address, instruction) –controls a number of more basic operations Some difference in expectation –can sequence a number of different tags/operations together -REMARC (Stanford, 1998) - Raw (MIT, 1997) - MorphoSys (UC Irvine, 2000) - MATRIX (MIT, 1997 - RaPiD (Reconfigurable Pipelined Datapaths) (University of Washington, 1996) -PipeRench (Carnegie Mellon, 1999) - DAPDNA-2 (IPFlex Inc., 2004?) ……… Examples: Coarse Grain RC See DAPDNA Handout

64. EECC722 - Shaaban #64 lec # 9 Fall 2006 10-23-2006 REMARC (Stanford, 1998) Array of “nano-processors” –16b, 32 instructions each –VLIW like execution, global sequencer Coprocessor interface (similar to GARP) –No direct array  memory VLIW/microcoded Model (paper RC-5)

65. EECC722 - Shaaban #65 lec # 9 Fall 2006 10-23-2006 REMARC Architecture Issue coprocessor rex –global controller sequences nano-processors –multiple cycles (microcode) Each nano-processor has own I-store (VLIW) Here array has 8 x 8 = 64 nano-processors Nano-processor (paper RC-5) (micro-coded) Micro-codeRAM

66. EECC722 - Shaaban #66 lec # 9 Fall 2006 10-23-2006 REMARC Results MPEG2 DES (paper RC-5)

67. EECC722 - Shaaban #67 lec # 9 Fall 2006 10-23-2006 Hybrid-Architecture RC Compute Models: Observation All single threaded –Limited to parallelism at: Instruction level (VLIW, bit-level) Data level (vector/stream/SIMD) –No task/thread level parallelism (TLP) Except for IO dedicated task parallel with processor task

68. EECC722 - Shaaban #68 lec # 9 Fall 2006 10-23-2006 Hybrid-Architecture RC Compute Models: Autonomous Coroutine Array task is decoupled from processor –Fork operation / join upon completion Array has own –Internal state –Access to shared state (memory) NAPA supports this to some extent –Task level, at least, with multiple devices Example: - OneChip (Toronto, 1998) Separate thread (paper RC-2)

69. EECC722 - Shaaban #69 lec # 9 Fall 2006 10-23-2006 OneChip (Toronto, 1998) Want array to have direct memory  memory operations Want to fit into programming model/ISA –without forcing exclusive processor/FPGA operation –allowing decoupled processor/array execution Key Idea: –FPGA operates on memory  memory regions –Make regions explicit to processor issue –scoreboard memory blocks (paper RC-2) To Check for dependency violations Hybrid-Architecture RC Compute Models:Autonomous Coroutine Hybrid-Architecture RC Compute Models: Autonomous Coroutine

70. EECC722 - Shaaban #70 lec # 9 Fall 2006 10-23-2006 OneChip Pipeline (paper RC-2)

71. EECC722 - Shaaban #71 lec # 9 Fall 2006 10-23-2006 OneChip Coherency (paper RC-2) RAWRAWWARWARWAWWAW

72. EECC722 - Shaaban #72 lec # 9 Fall 2006 10-23-2006 OneChip Instructions Basic Operation is: –FPGA MEM[Rsource]  MEM[Rdst] block sizes powers of 2 Supports 14 “loaded” functions –DPGA/contexts so 4 can be cached (paper RC-2) Memory to memory Source Memory Block Base address Destination Memory Block Base address

73. EECC722 - Shaaban #73 lec # 9 Fall 2006 10-23-2006 OneChip Basic op is: FPGA MEM  MEM No state between these ops coherence is that ops appear sequential could have multiple/parallel FPGA Compute units –scoreboard with processor and each other Can’t chain FPGA operations? (paper RC-2)

74. EECC722 - Shaaban #74 lec # 9 Fall 2006 10-23-2006 Summary Several different models and uses for a “Reconfigurable Processor”: –On computational kernels seen the benefits of coarse-grain interaction –GARP, REMARC, OneChip –Missing: More full application (multi-application) benefits of these architectures... Exploit density and expressiveness of fine-grained, spatial operations Number of ways to integrate cleanly into processor architecture…and their limitations