1. © Digital Integrated Circuits 2nd Devices VLSI Devices  Intuitive understanding of device operation  Fundamental analytic models  Manual Models  Spice Models  Secondary and deep-sub-micron effects  Junction Diode and FET  Resistor and Capacitor

2. © Digital Integrated Circuits 2nd Devices The Diode Occurs as parasitic element in Digital ICs

3. © Digital Integrated Circuits 2nd Devices Depletion Region

4. © Digital Integrated Circuits 2nd Devices Forward Bias x p n0 n p0 -W 1 W 2 0 p n ( W 2 ) n-region p-region L p diffusion Forward Bias usually avoided in Digital ICs

5. © Digital Integrated Circuits 2nd Devices Reverse Bias Diode Isolation Mode

6. © Digital Integrated Circuits 2nd Devices Diode Current

7. © Digital Integrated Circuits 2nd Devices Models for Manual Analysis

8. © Digital Integrated Circuits 2nd Devices Junction Capacitance

9. © Digital Integrated Circuits 2nd Devices Diffusion Capacitance (Forward Bias)

10. © Digital Integrated Circuits 2nd Devices Secondary Effects –25.0–15.0–5.05.0 V D (V) –0.1 I D ( A ) 0.1 0 0 Avalanche Breakdown

11. © Digital Integrated Circuits 2nd Devices Diode Model (Manual Analysis)

12. © Digital Integrated Circuits 2nd Devices SPICE Parameters  Transit time models charge storage

13. © Digital Integrated Circuits 2nd Devices What is a Transistor?  Resistor is poor model in saturation– current source  Source and Drain are symmetric  N-channel: Source is most negative of the two  P-channel: Source is most positive of the two  Four Modes:  Off (leakage current only)  Sub-Threshold (exponential)  Linear (Resistive)  Saturation (Current Source) A Switch!

14. © Digital Integrated Circuits 2nd Devices The MOS Transistor Polysilicon Aluminum

15. © Digital Integrated Circuits 2nd Devices MOS Transistors - Types and Symbols D S G D S G G S DD S G NMOS Enhancement NMOS PMOS Depletion Enhancement B NMOS with Bulk Contact

16. © Digital Integrated Circuits 2nd Devices Threshold Voltage: Concept

17. © Digital Integrated Circuits 2nd Devices The Threshold Voltage

18. © Digital Integrated Circuits 2nd Devices The Body Effect

19. © Digital Integrated Circuits 2nd Devices Quadratic Relationship 00.511.522.5 0 1 2 3 4 5 6 x 10 -4 V DS (V) I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V ResistiveSaturation V DS = V GS - V T Current-Voltage Relation

20. © Digital Integrated Circuits 2nd Devices Transistor in Linear

21. © Digital Integrated Circuits 2nd Devices Transistor in Saturation Pinch-off Region

22. © Digital Integrated Circuits 2nd Devices Current-Voltage Relations Long-Channel Device

23. © Digital Integrated Circuits 2nd Devices A model for manual analysis

24. © Digital Integrated Circuits 2nd Devices Current-Voltage Relations: Deep-Submicron FET Linear Relationship -4 V DS (V) 00.511.522.5 0 0.5 1 1.5 2 2.5 x 10 I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Early Saturation

25. © Digital Integrated Circuits 2nd Devices Velocity Saturation  (V/µm)  c = 1.5  n ( m / s )  sat = 10 5 Constant mobility (slope = µ) Constant velocity

26. © Digital Integrated Circuits 2nd Devices Perspective I D Long-channel device Short-channel device V DS V DSAT V GS - V T V GS = V DD

27. © Digital Integrated Circuits 2nd Devices I D versus V GS 00.511.522.5 0 1 2 3 4 5 6 x 10 -4 V GS (V) I D (A) 00.511.522.5 0 0.5 1 1.5 2 2.5 x 10 -4 V GS (V) I D (A) quadratic linear Long Channel Short Channel

28. © Digital Integrated Circuits 2nd Devices I D versus V DS -4 V DS (V) 00.511.522.5 0 0.5 1 1.5 2 2.5 x 10 I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V 00.511.522.5 0 1 2 3 4 5 6 x 10 -4 V DS (V) I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V ResistiveSaturation V DS = V GS - V T Long ChannelShort Channel

29. © Digital Integrated Circuits 2nd Devices A unified model for manual analysis S D G B

30. © Digital Integrated Circuits 2nd Devices Simple Model versus SPICE V DS (V) I D (A) Velocity Saturated Linear Saturated V DSAT =V GT V DS =V DSAT V DS =V GT

31. © Digital Integrated Circuits 2nd Devices A PMOS Transistor -2.5-2-1.5-0.50 -0.8 -0.6 -0.4 -0.2 0 x 10 -4 V DS (V) I D (A) VGS = -1.0V VGS = -1.5V VGS = -2.0V VGS = -2.5V

32. © Digital Integrated Circuits 2nd Devices Transistor Model for Manual Analysis 0.5  m VtGammaVd(sat) k’ (  A/V2) Lambda NMOS0.7-0.80.483.150-600.04* PMOS-0.91- -0.97 0.59-6.5-17- -20 -0.07*

33. © Digital Integrated Circuits 2nd Devices The Transistor as a Switch

34. © Digital Integrated Circuits 2nd Devices The Transistor as a Switch

35. © Digital Integrated Circuits 2nd Devices The Transistor as a Switch

36. © Digital Integrated Circuits 2nd Devices MOS Capacitances Dynamic Behavior

37. © Digital Integrated Circuits 2nd Devices Dynamic Behavior of MOS Transistor

38. © Digital Integrated Circuits 2nd Devices The Gate Capacitance t ox n + n + Cross section L Gate oxide x d x d L d Polysilicon gate Top view Gate-bulk overlap Source n + Drain n + W

39. © Digital Integrated Circuits 2nd Devices Gate Capacitance Cut-off ResistiveSaturation Most important regions in digital design: saturation and cut-off

40. © Digital Integrated Circuits 2nd Devices Gate Capacitance Capacitance as a function of VGS (with VDS = 0) Capacitance as a function of the degree of saturation

41. © Digital Integrated Circuits 2nd Devices Diffusion Capacitance Bottom Side wall Channel Source N D Channel-stop implant N A 1 SubstrateN A W x j L S

42. © Digital Integrated Circuits 2nd Devices Junction Capacitance

43. © Digital Integrated Circuits 2nd Devices Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest

44. © Digital Integrated Circuits 2nd Devices MOS Capacitances in 0.25/0.5  m CMOS processes 0.5um AMI/C5 C ox fF/  m 2 C 0 fF/  m C j fF/  m 2 mjmj bVbV C jsw fF/  m m jsw  bsw V NMOS2.50.200.440.340.900.280.350.89 PMOS2.40.280.730.50.910.330.320.90

45. © Digital Integrated Circuits 2nd Devices The Sub-Micron MOS Transistor  Threshold Variations  Subthreshold Conduction  Parasitic Resistances

46. © Digital Integrated Circuits 2nd Devices Threshold Variations V T L Long-channel threshold LowV DS threshold Threshold as a function of the length (for lowV DS ) Drain-induced barrier lowering (for lowL) V DS V T

47. © Digital Integrated Circuits 2nd Devices Sub-Threshold Conduction 00.511.522.5 10 -12 10 -10 10 -8 10 -6 10 -4 10 -2 V GS (V) I D (A) VTVT Linear Exponential Quadratic Typical values for S: 60.. 100 mV/decade The Slope Factor S is  V GS for I D 2 / I D 1 =10

48. © Digital Integrated Circuits 2nd Devices Sub-Threshold I D vs V GS V DS from 0 to 0.5V

49. © Digital Integrated Circuits 2nd Devices Sub-Threshold I D vs V DS V GS from 0 to 0.3V

50. © Digital Integrated Circuits 2nd Devices Summary of MOSFET Operating Regions  Strong Inversion V GS > V T  Linear (Resistive) V DS < V DSAT  Saturated (Constant Current) V DS  V DSAT  Weak Inversion (Sub-Threshold) V GS  V T  Exponential in V GS with linear V DS dependence

51. © Digital Integrated Circuits 2nd Devices Parasitic Resistances

52. © Digital Integrated Circuits 2nd Devices Latch-up

53. © Digital Integrated Circuits 2nd Devices Future Perspectives 25 nm FINFET MOS transistor

54. © Digital Integrated Circuits 2nd Devices Problems HW3 1. Rabaey Chap. 3 on-line problems: 2, 3(do not do the spice simulation), 6, 9(L=0.5um) 2. Consider an inverter built with 1/0.5 (nmos W/L) and 2/0.5 (pmos) transistors. Draw a sue schematic for the inverter driving a 10fF load capacitor (other terminal is grounded). Using your model for the AMI FET transistors, determine the peak current flowing into the FET after both an abrupt rising and falling edge on the inverter input, given a supply voltage of 3.3 Volts and using the Mosis extracted parameters from the MOSIS or the class website. Simulate these transitions using spice from the Sue schematic. 3. Complete the Max layout of the full adder cells and build a schematic in sue for each cell and for an 8-bit ripple carry adder. Be sure to use the same transistor sizes in the schematic as you had in your layout. Simulate the adder for the following transition: a=0->1, b=255 Plot the sum and carry outputs and estimate the total carry chain delay and delay per stage.