1. Xilinx CPLDs and FPGAs Lecture L1.1

2. CPLDs and FPGAs XC9500 CPLD Spartan II FPGA Virtex FPGA

3. XC9500 CPLDs 5 volt in-system programmable (ISP) CPLDs 5 ns pin-to-pin 36 to 288 macrocells (6400 gates) Industry’s best pin- locking architecture 10,000 program/erase cycles Complete IEEE 1149.1 JTAG capability Function Block 1 JTAG Controller Function Block 2 I/O Function Block 4 3 Global Tri-States 2 or 4 Function Block 3 I/O In-System Programming Controller FastCONNECT Switch Matrix JTAG Port 3 I/O Global Set/Reset Global Clocks I/O Blocks 1

4. XC9500 Function Block To FastCONNECT From FastCONNECT 2 or 4 3 Global Tri-State Global Clocks I/O 36 Product- Term Allocator Macrocell 1 AND Array Macrocell 18 Each function block is like a 36V18 !

5. XC9500 Product Family 9536 Macrocells Usable Gates t PD (ns) Registers Max I/O 3672108144216 8001600240032004800 57.5 10 3672108144216 3472108133166 Packages VQ44 PC44 PC84 TQ100 PQ100 PC84 TQ100 PQ100 PQ160 PQ100 PQ160 288 6400 10 288 192 HQ208 BG352 PQ160 HQ208 BG352 957295108951449521695288

6. Xilinx 95108 6 function blocks –Each contains 18 macro cells –Each macro cell behaves like a GAL32V18 AND-OR array for sum-of-products 32 inputs and 18 outputs

7. Architecture of the Xilinx XC95108 CPLD

8. Each Xilinx 95108 macrocell contains a D flip-flop Controlled inverter

9. Each Xilinx 95108 macrocell contains a D flip-flop Note asynchronous preset x Note asynchronous reset y z

10. CPLDs and FPGAs XC9500 CPLD Spartan II FPGA Virtex FPGA

11. Block diagram of Xilinx Spartan IIE FPGA

12. Each Spartan IIE CLB contains two of these CLB slices

13. Xilinx Spartan-II FPGAs

14. Block RAM

16. Delay-Locked Loop

17. Phase-Locked Loop

18. CPLDs and FPGAs XC9500 CPLD Spartan II FPGA Virtex FPGA

19. Virtex FPGAs For info on Virtex 1000 boards, see http://www.zarx.info/

20. Virtex-II FPGAs

21. Virtex-II Pro FPGAs